Semiconductor Gate Barrier Planarization via Gas Cluster Ion Beam
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Solution Overview
Problem
The existing semiconductor fabrication methods face challenges in achieving stable electrical performance due to uneven capping layer deposition and mechanical grinding processes, which can lead to short-circuit failures and instability in ultra-large-scale integrated circuits.
Innovation Solution
A method involving etching back gate structures, forming a barrier layer, and using a gas cluster ion beam (GCIB) process to planarize and control the thickness of the sacrificial and barrier layers, ensuring a stable and even surface for improved semiconductor device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capping layer is formed over the gate structure to prevent short-circuit failure, then the reliability of the gate connection is improved, but the manufacturing precision and electrical performance stability deteriorate due to uneven deposition and mechanical grinding
Solution Approach 1:
The patent replaces the mechanical grinding process with a chemical etching process using buffered oxide etch (BOE) solution. This substitution eliminates the mechanical contact that causes uneven surface treatment, allowing the capping layer to be planarized chemically with better uniformity and precision while maintaining the protective function against short-circuit failures
Solution Approach 2:
The patent changes the deposition parameters of the capping layer by forming it at a controlled thickness (e.g., 50-200 nm) and then using controlled chemical etching to remove excess material. This parameter control ensures uniform thickness distribution across the wafer surface, improving manufacturing precision while maintaining the reliability function of preventing short-circuits
2Adaptability or versatility
If the circuit density is increased to achieve ultra-large-scale ICs, then the functionality and integration level are improved, but the available wafer area for connection wires is reduced
Solution Approach 1:
The patent introduces a vertical dimension by forming multi-layer intermetallic interconnection structures with plugs extending through dielectric layers. This three-dimensional interconnection approach allows more connection wires to be packed into the same wafer area by utilizing the vertical space, thereby maintaining circuit density while providing sufficient connection pathways
Solution Approach 2:
The patent implements nested interconnection structures where plugs are formed within dielectric layers that contain gate structures, and multiple metal layers are stacked vertically. This nesting arrangement maximizes the use of available wafer area by organizing connection wires in multiple hierarchical levels rather than spreading them out in a single plane
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The GCIB process effectively controls the thickness of the barrier layer, enhancing the stability and performance of semiconductor devices by preventing short-circuit failures and ensuring uniformity, thereby improving the overall electrical performance.
Implementation Method 1
using a gas cluster ion beam (GCIB) process to planarize the sacrificial layer and the barrier layer
Implementation Method 2
etching back each gate structure of a plurality of gate structures to form an opening
Data Source
AI summary
A method of forming a method of forming a semiconductor device includes providing a semiconductor structure, etching back each gate structure of a plurality of gate structures to form an opening, forming a barrier layer over the dielectric layer, forming a sacrificial layer over the barrier layer, planarizing the sacrificial layer till a surface of the sacrificial layer is substantially flat, and using a gas cluster ion beam (GCIB) process to planarize the sacrificial layer and the barrier layer, and to remove the sacrificial layer and to provide a planarized barrier layer. The semiconductor structure includes a semiconductor substrate, a fin, the plurality of gate structures, and a dielectric layer over the semiconductor substrate between adjacent gate structures. A top of the dielectric layer is coplanar with a top of each of the plurality of gate structures.