Semiconductor Gate With Bulbous And Flattened Grooves
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Solution Overview
Problem
Semiconductor devices with saddle fin-shaped channels face challenges in maintaining threshold voltage reliability due to intensified electric fields and increased junction leakage, leading to degraded refresh characteristics and shortened retention times.
Innovation Solution
A semiconductor device with recess parts having bulbous-shaped first grooves and vertically extending second grooves, featuring a double-layered gate insulation layer in the first grooves and a single-layered structure in the second grooves, along with a stack-like gate structure, is designed to reduce gate-induced drain leakage and enhance retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the concentration of boron in the channel is increased to maintain threshold voltage, then the threshold voltage reliability is improved, but the electric fields in junction areas are intensified and junction leakage increases
Solution Approach 1:
The gate insulation layer is designed with non-uniform thickness, being thicker at the front and rear surfaces of the gate forming area and thinner at the bottom surface. This local variation in insulation thickness allows different regions to serve different functions: the thicker front and rear surfaces reduce GIDL while the thinner bottom surface maintains effective threshold voltage control, thereby resolving the contradiction between threshold voltage reliability and junction leakage.
Solution Approach 2:
The invention changes the thickness parameter of the gate insulation layer from a uniform structure to a non-uniform structure with specific thickness variations. The gate insulation layer has a first thickness at the front and rear surfaces and a second thickness at the bottom surface, where the first thickness is greater than the second thickness. This parameter change optimizes both threshold voltage control and GIDL reduction simultaneously.
2Length of moving object
If conventional saddle fin-shaped channel structure is used, then effective channel length is achieved, but refresh characteristics degrade and retention time is shortened
Solution Approach 1:
The gate insulation layer thickness parameter is changed from uniform to non-uniform distribution. The first thickness at the front and rear surfaces is greater than the second thickness at the bottom surface. This parameter optimization reduces GIDL current and improves refresh characteristics, thereby extending retention time while maintaining the effective channel length of the saddle fin structure.
Data Source
AI summary
A semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous are is presented. The semiconductor device includes a semiconductor substrate, an isolation layer, a gate insulation layer, and gates. The semiconductor substrate has recess parts that have first grooves which have bulbous-shaped profiles and second vertically flattened profile grooves which extend downward from the first grooves. The gates are formed in the recess parts in which the gate insulation layer is double layered in the bulbous profile areas and is single layered in the flattened profile areas.