Semiconductor Gate Insulating Cap Layer for Contact Reliability
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face issues of electric shorting between source/drain contact plugs and gate electrodes, and high contact resistivity due to the small critical dimension and landing area of gate contact plugs, which can lead to device failure.
Innovation Solution
A semiconductor structure is designed with an insulating cap layer that is inwardly recessed and has a concave top surface, with varying thicknesses above different portions of the gate electrode, and is positioned atop a spacer or contact etching stop layer, to prevent shorting and reduce contact resistivity by providing a larger landing area for gate contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulating cap layer is disposed on the gate to act as a hard mask during the S/D contact hole etching process, then the gate electrode will not be etched and exposed, and the short between the S/D contact plug and the gate electrode can be prevented, but it may cause extra difficulty for the gate contact hole etching
Solution Approach 1:
The insulating cap layer is configured with non-uniform thickness: a first thickness over the gate electrode and a second thickness over the spacer, where the first thickness is less than the second thickness. This local differentiation allows the gate contact hole etching to penetrate through the thinner region to reach the gate electrode, while the thicker region prevents etching of the S/D contact holes, thus resolving the contradiction between preventing shorts and enabling gate contact formation
Solution Approach 2:
The insulating cap layer is segmented into different thickness regions corresponding to different functional areas: a thinner region over the gate electrode for gate contact access and a thicker region over the spacer for S/D contact protection. This segmentation allows each region to serve its specific function simultaneously
2Productivity
If the critical dimension and spacing of contact plugs are scaled down to reduce chip size, then chip size is reduced, but electric shorting between gate and S/D contact and high contact resistivity occur
Solution Approach 1:
The solution moves from two-dimensional scaling (reducing CD and spacing) to three-dimensional structural differentiation (varying thickness of insulating cap layer in the vertical dimension and different horizontal regions). By utilizing the thickness dimension and spatial positioning, the patent achieves both miniaturization and reliable electrical contact without shorting
3Reliability
If the insulating cap layer is made uniformly thick to prevent shorting, then shorting is prevented, but the landing area for gate contact plug is reduced and contact resistivity increases
Solution Approach 1:
The insulating cap layer exhibits local quality variation with different thicknesses in different regions: thinner over the gate electrode to allow proper contact formation and larger landing area, and thicker over the spacer to ensure shorting prevention. This local differentiation simultaneously achieves both objectives
Data Source
AI summary
A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.