Semiconductor Device Gate Capacitance Reduction via Dummy Electrode
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Solution Overview
Problem
In bipolar semiconductor devices, reducing gate capacitance to increase switching speed while maintaining withstand voltage is challenging, especially when the oxide film covering the polysilicon region is poorly formed, leading to leak current between the collector and emitter electrodes.
Innovation Solution
The semiconductor device incorporates a conductive region of a first conductive type, separated from the second semiconductor region by a second conductive region of opposite type, reducing the number of gate electrodes and ensuring the conductive region is electrically connected to the same potential as the main electrode, preventing potential distribution disturbances and leak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of gate electrodes is reduced to decrease gate capacitance, then switching speed is improved, but the potential distribution in the semiconductor device is disturbed and withstand voltage decreases
Solution Approach 1:
A polysilicon region is introduced as an intermediary element between the emitter electrode and the drift region. This polysilicon region is electrically connected to the emitter electrode and positioned in the second trench, acting as a mediator to maintain proper potential distribution without requiring additional gate electrodes, thus preserving withstand voltage while enabling gate capacitance reduction
Solution Approach 2:
The polysilicon region is electrically connected to the emitter electrode to establish equipotential conditions. By maintaining the same potential as the emitter electrode, the polysilicon region prevents potential distribution disturbances in the semiconductor device when gate electrodes are reduced, thereby maintaining withstand voltage
2Speed
If an n-type polysilicon region is connected with an n-type drift region by a thin oxide film to reduce gate capacitance, then switching speed is improved, but when the oxide film is formed poorly, carrier flows from collector to emitter via the polysilicon region causing leak current
Solution Approach 1:
A p-type conductive region is formed beforehand between the n-type polysilicon region and the n-type drift region as a preventive measure. This p-type region acts as a cushioning barrier that blocks carrier flow even if the oxide film is poorly formed, preventing leak current from flowing from the collector to the emitter through the polysilicon region
Solution Approach 2:
A p-type conductive region is introduced as an intermediary barrier between the n-type polysilicon region and the n-type drift region. This intermediary p-type region blocks the flow of carriers that would otherwise occur through the poorly formed oxide film, preventing leak current while maintaining the benefits of reduced gate capacitance
Data Source
AI summary
An object of the present application is to reduce the gate capacitance without lowering the withstand voltage of a semiconductor device and prevent generation of a leak current between main electrodes even when an oxide film is formed poorly. A semiconductor device of the present application comprises a gate electrode and a dummy gate electrode. The gate electrode is insulated from an emitter electrode and faces a part of a body region via an insulating film, the part of the body region separating a drift region and an emitter region from each other. The dummy gate electrode is electrically connected with the emitter electrode and is connected with the drift region and the body region via the insulating film. At least a part of the dummy gate electrode comprises a first conductive region of the same type as the drift region. In the dummy gate electrode, the emitter electrode is separated from the drift region by the first conductive region.