Semiconductor Gate Structure for Lower Gate-Source Capacitance
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Solution Overview
Problem
Conventional semiconductor devices experience significant gate-source capacitance (CGS) due to the entire side surface of the gate electrode being in contact with the n-type source region, which affects switching time and device performance.
Innovation Solution
A semiconductor device is designed with a parasitic capacitance reduction region formed in contact with the source region and the gate electrode through an insulating film, featuring a higher resistance value than the source region, which reduces the gate-source capacitance by creating a series connection with the gate insulating film capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire side surface of the gate electrode is in contact with the n-type source region, then the gate electrode can be properly formed and connected, but a large gate-source capacitance CGS is generated which slows down switching time
Solution Approach 1:
The source region is divided into two distinct parts: a first n-type source region that contacts the gate electrode for proper electrical connection, and a second n-type source region that is separated from the gate electrode by an insulating film. This segmentation allows the gate electrode to be properly connected while preventing excessive capacitance formation, thereby resolving the contradiction between reliable connection and fast switching time.
Solution Approach 2:
An insulating film is introduced as an intermediary layer between the second n-type source region and the gate electrode. This intermediary prevents direct contact and reduces the gate-source capacitance CGS, while still allowing the first source region to provide necessary electrical connection. The insulating film acts as a mediator that balances connection reliability with switching speed.
2Reliability
If the n-type source region is fully in contact with the gate electrode side surface, then electrical connection is ensured, but the gate-source capacitance CGS increases reducing device performance
Solution Approach 1:
The source region is segmented into contact and non-contact portions relative to the gate electrode. The first n-type source region maintains electrical connection for reliability, while the second n-type source region is isolated by an insulating film to reduce capacitance. This segmentation enables the device to achieve both reliable connection and high performance.
Solution Approach 2:
Different regions of the source are given different properties: the first n-type source region has direct contact with the gate electrode for electrical connection, while the second n-type source region has an insulating film between it and the gate electrode to reduce capacitance. This local differentiation of contact properties allows simultaneous achievement of connection reliability and device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases the gate-source capacitance, thereby shortening the switching time of the semiconductor device and improving its operational efficiency.
Implementation Method 1
a parasitic capacitance reduction region 11 which is in contact with the source region 3 and in contact with the gate electrode 21 through the gate insulating film 19
Data Source
AI summary
A semiconductor device includes: a substrate; a source region formed on a main surface of the substrate; a well region electrically connected to the source region; a drift region in contact with the well region; a drain region in contact with the drift region; a first electrode electrically connected to the source region; a second electrode electrically connected to the drain region; a third electrode formed in contact with the source region, the well region, and the drift region through an insulating film; and a parasitic capacitance reduction region formed in contact with the source region and in contact with the third electrode through the insulating film and having a higher resistance value than that of the source region.