Semiconductor Gate Structure for Parasitic Capacitance Reduction

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to reduce parasitic capacitance between gate wiring and substrate while implementing a gate last process for Surrounding Gate Transistors (SGT), which requires careful consideration of metal gate contamination and high-temperature processes, especially when forming pillar-shaped semiconductor layers.

Innovation Solution

A method involving the formation of fin-shaped and pillar-shaped semiconductor layers, followed by the deposition of insulating films, polysilicon gate electrodes, and metal gate wiring, where the polysilicon gate is formed before the metal gate to minimize parasitic capacitance and facilitate a gate last process, including steps like etching, diffusion layer formation, and silicide creation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a metal gate is formed after a high-temperature process (gate last process), then the metal gate process and high-temperature process can be satisfied simultaneously, but the process complexity increases due to considerations of metal contamination and high-temperature process compatibility

Engineering Contradiction:

Improvecompatibility of metal gate process and high-temperature processVSAvoidprocess complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The gate formation process is divided into two distinct stages: first forming a polysilicon gate structure, then forming the metal gate on top of it. This segmentation allows each material to be optimized for its specific function while maintaining process compatibility

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The polysilicon gate is formed in advance before the metal gate. This preliminary action creates a foundation structure that protects against metal contamination during high-temperature processes while still allowing the final metal gate to be formed for optimal electrical performance

Inventive Principle:

Principle #10Preliminary action

2Object-affected harmful factors

If a first insulating film is formed around the fin-shaped semiconductor layer, then the parasitic capacitance between gate wiring and substrate is decreased, but the manufacturing process becomes more complex due to additional etching back steps

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidmanufacturing process simplicity

Core Design Contradiction:

Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The insulating film is extended into the vertical dimension surrounding the fin-shaped semiconductor layer, creating a three-dimensional isolation structure that effectively reduces parasitic capacitance between the gate wiring and substrate

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If the polysilicon gate is exposed by chemical mechanical polishing and etched, then the metal gate can be deposited, but the process time increases due to additional polishing and etching steps

Engineering Contradiction:

Improvemetal gate deposition capabilityVSAvoidprocess time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The polysilicon gate is formed as a preliminary structure that serves as both a functional gate and a protective layer. This preliminary formation eliminates the need for subsequent polishing and etching steps that would otherwise be required to expose the gate for metal deposition

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively decreases parasitic capacitance and allows for a gate last process in SGT manufacturing, simplifying the process by forming polysilicon gates before metal gates, thus addressing the complexities of metal contamination and high-temperature processes.

Implementation Method 1

etching a semiconductor substrate to form a fin-shaped semiconductor layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

depositing a first insulating film around the fin-shaped semiconductor layer

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Implementation Method 3

the polysilicon gate is exposed by chemical mechanical polishing

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS10438836B2Method for manufacturing a semiconductor device

Publication Date: 2019.10.08 UNISANTIS ELECTRONICS SINGAPORE PTE LTD

AI summary

A method for manufacturing a semiconductor device includes etching a semiconductor substrate to form a fin-shaped semiconductor layer. After forming the fin-shaped semiconductor layer, a first insulating film is deposited around the fin-shaped semiconductor layer. The first insulating film is etched back to expose an upper portion of the fin-shaped semiconductor layer and a second resist is formed so as to be perpendicular to the fin-shaped semiconductor layer. The fin-shaped semiconductor layer is etched to form a pillar-shaped semiconductor layer, such that a portion where the fin-shaped semiconductor layer and the second resist intersect at right angles defines the pillar-shaped semiconductor layer.