Semiconductor Gate Capping Layer Deposition Control
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Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in achieving precise control over capping layer deposition and epitaxial growth, leading to reduced integration density and carrier mobility due to incomplete removal of capping layers from sidewalls and spacers, which affects the formation of source/drain regions.
Innovation Solution
A method involving high-density plasma processes with zero or low step coverage to form capping layers only on top surfaces of gate structures and spacers, allowing for selective epitaxial growth without capping layer deposition on sidewalls, enabling complete removal and enhancing integration density and carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a capping layer is formed by conventional plasma process, then the capping layer covers the gate structures, but the capping layer also deposits on sidewalls and spacers, making complete removal difficult and reducing integration density
Solution Approach 1:
The patent applies local quality by creating different deposition characteristics in different spatial regions. The high-density plasma process is configured to deposit capping layer material preferentially on horizontal surfaces (gate tops) while minimizing deposition on vertical surfaces (sidewalls). This is achieved by controlling plasma parameters such as pressure, power, and gas flow to create anisotropic deposition, where the deposition rate and coverage vary by location and surface orientation.
Solution Approach 2:
The patent employs parameter changes by modifying plasma process parameters to achieve zero or low step coverage. Specific parameters adjusted include plasma power (increased to enhance surface mobility and reduce sidewall deposition), pressure (optimized to control mean free path and deposition uniformity), and gas composition (ratios of silane to oxygen or nitrogen adjusted to control deposition rate and film properties). These parameter changes enable selective deposition only where needed.
2Manufacturing precision
If capping layer is completely removed from sidewalls, then epitaxial growth can proceed uniformly, but conventional processes cannot achieve complete removal due to long incubation times
Solution Approach 1:
The patent applies preliminary action by forming the capping layer with inherently low or zero step coverage during the deposition process itself. Rather than attempting to remove capping layer material from sidewalls after deposition, the process is designed to prevent sidewall deposition in the first place. This preliminary prevention eliminates the need for extended incubation times and complex removal processes, as there is minimal or no capping layer material to remove from vertical surfaces.
3Manufacturing precision
If high-density plasma process is used to form capping layer with zero step coverage, then sidewalls remain clean for epitaxial growth, but process parameters must be precisely controlled
Solution Approach 1:
The patent employs parameter changes by establishing specific ranges for plasma process parameters that reliably produce zero or low step coverage. Key parameters include plasma power (typically 50-500 watts), pressure (0.1-10 Torr), and gas composition ratios (silane to oxygen or nitrogen). By defining these parameter ranges, the process achieves consistent anisotropic deposition without requiring overly complex real-time control systems. The interplay between these parameters creates a robust process window that maintains low step coverage across normal process variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves integration density by preventing gap reduction between gate structures and increases epitaxial layer volume, thereby enhancing carrier mobility and transistor performance.
Implementation Method 1
forming a first capping layer on the substrate by a first high density plasma process
Implementation Method 2
forming a first epitaxial layer to fill the first trench
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.