Semiconductor Gate Structure CMP Protection
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Solution Overview
Problem
In high-voltage regions of semiconductor devices, the metal gate formed during the CMP process is often lost due to protrusion of the gate dielectric layer, leading to inferior device performance and reduced gate capacitance.
Innovation Solution
A method involving the formation of polysilicon gate structures on both logic and high-voltage regions, followed by the creation of an interlayer dielectric layer and a patterned hard mask on the high-voltage region, which protects the polysilicon gate from CMP removal, allowing for the deposition of work function metal layers and low resistance metal layers to form metal gates on the logic region while maintaining the polysilicon gate on the high-voltage region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate dielectric layer on high-voltage region protrudes from the substrate surface, then the metal gate formed on high-voltage region becomes higher than the metal gate on low-voltage region, but a large portion of the metal gate on high-voltage region is lost by CMP process
Solution Approach 1:
The substrate is divided into logic region and high-voltage region, with different gate structures formed on each region. The high-voltage region uses a protruding gate structure that is protected during CMP, while the logic region uses a standard planar gate structure. This segmentation allows each region to have optimized characteristics without interfering with the other.
Solution Approach 2:
The gate dielectric layer on the high-voltage region is formed to protrude from the substrate surface before the metal gate deposition and CMP processes. This preliminary protrusion ensures that the metal gate on the high-voltage region maintains its height and functionality even after CMP removes excess material from the logic region.
2Ease of manufacture
If polysilicon gate is used, then fabrication is simple, but boron penetration and depletion effect increase equivalent thickness of gate dielectric layer, reduce gate capacitance, and worsen driving force
Solution Approach 1:
Different gate materials are used in different regions: metal gate with high-k dielectric is used in the logic region to achieve high performance and driving force, while polysilicon gate is retained in the high-voltage region where it is sufficient and simpler. This local differentiation optimizes each region's characteristics.
Solution Approach 2:
The logic region employs a composite structure of metal gate electrode combined with high-k dielectric layer, which provides both the electrical performance benefits of metal and the dielectric benefits of high-k materials, overcoming the limitations of conventional polysilicon gates.
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.