Semiconductor Gate Patterns with Connection Lines
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Solution Overview
Problem
Semiconductor IC devices face challenges in improving current drivability due to gate patterns with step differences that are prone to damage during fabrication, leading to increased parasitic capacitances and internal resistances, especially with the shrinking design rules.
Innovation Solution
The semiconductor IC device design includes gate patterns with a step difference in the cell array and peripheral circuit regions, along with connection lines formed using distinct process operations, which enhance current drivability by reducing parasitic capacitances and internal resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate patterns are simultaneously formed under and on the top surface of the active region to simplify fabrication, then manufacturing complexity is reduced, but the gate patterns become vulnerable to damage and undesired shaping due to step differences
Solution Approach 1:
The fabrication process is divided into separate stages: first forming the cell array gate pattern under the active region, then forming the peripheral circuit gate pattern on the top surface in a subsequent step. This segmentation allows each gate pattern to be formed under optimized conditions without the other present, eliminating the step difference vulnerability while maintaining process simplicity.
Solution Approach 2:
The cell array gate pattern is formed in advance before the peripheral circuit gate pattern. This preliminary action allows the first gate pattern to be fully established and stabilized before the second gate pattern formation begins, preventing damage from step differences during fabrication.
2Productivity
If design rules are reduced to increase device density, then productivity is improved, but gate patterns with step differences suffer from increased parasitic capacitances and internal resistances
Solution Approach 1:
By segmenting the gate pattern formation into separate steps, each gate pattern can be optimized independently for its specific location and function. This eliminates the parasitic effects caused by step differences while maintaining the benefits of reduced design rules and increased device density.
Solution Approach 2:
The formation timing parameter is changed for different gate patterns - cell array gates are formed in an earlier process step while peripheral circuit gates are formed later. This parameter change eliminates step differences and reduces parasitic capacitances and internal resistances, improving current drivability while maintaining high device density.
Data Source
AI summary
Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.