Semiconductor Gate Contact via Alignment Structure
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Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges in reducing feature sizes below 28 nm, leading to area inefficiencies and potential electrical shorts due to the placement of gate contacts outside the oxide diffusion region, which can result in poor device performance or non-operation.
Innovation Solution
A method is introduced that involves forming an alignment structure on the top surface of the gate electrode, surrounding it with an inter-layer dielectric, and then removing the alignment structure to expose the gate electrode, allowing for the formation of a conductor in contact with the gate electrode without covering the source/drain regions, thus preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contacts are placed outside the oxide diffusion region to avoid electrical shorts, then device reliability is improved, but area efficiency deteriorates
Solution Approach 1:
The patent transitions from conventional planar contact placement to a vertical three-dimensional structure. The gate contact is positioned vertically above the gate electrode through a via structure, allowing electrical connection without lateral extension into the oxide diffusion region. This vertical dimensionality change resolves the contradiction by achieving both reliability (no electrical shorts) and area efficiency (compact footprint).
Solution Approach 2:
The gate contact structure is nested within the vertical stack above the gate electrode. The contact via is formed through the inter-layer dielectric and aligned with the gate electrode, creating a nested configuration where the contact is contained within the vertical projection of the gate structure. This nesting approach eliminates the need for lateral placement outside the oxide diffusion region while maintaining electrical connectivity.
2Adaptability or versatility
If feature sizes are reduced below 28 nm to increase device functionality, then device integration is improved, but manufacturing precision deteriorates
Solution Approach 1:
An alignment structure is formed on the gate electrode before removing the inter-layer dielectric. This preliminary alignment structure serves as a guide for subsequent etching processes, ensuring precise positioning of the contact via even at sub-28 nm dimensions. The alignment structure is removed after serving its guiding function, leaving a precisely positioned contact structure without requiring high-precision lateral alignment throughout the entire process.
Solution Approach 2:
The alignment structure acts as an intermediary element that facilitates precise contact formation. It is temporarily introduced to guide the etching process, then removed after completing its alignment function. This intermediary approach decouples the precision requirement from the final structure, allowing standard manufacturing processes to achieve sub-28 nm precision.
3Manufacturing precision
If alignment structure is used to position gate conductor accurately, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The alignment structure is extracted as a separate, temporary component from the final device structure. It is formed, used for alignment, and then completely removed. This extraction approach allows the alignment function to be performed without permanently adding structural complexity to the device. The alignment structure serves its purpose and is discarded, leaving only the essential gate contact structure.
Solution Approach 2:
The alignment structure is discarded after completing its alignment function. The process recovers precision during fabrication but does not retain the alignment structure in the final device. This discarding approach resolves the contradiction by achieving high manufacturing precision through a temporary structure that is removed before final device completion, thus avoiding permanent complexity increase.
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.