Semiconductor Device Gate Contact With Insulation Spacer
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing parasitic capacitance between contact plugs and gates, which affects the performance and efficiency of transistors, particularly in finFET and planar transistor designs.
Innovation Solution
The semiconductor device incorporates a second contact plug that contacts the upper surface of the gate electrode between first contact plugs, with an insulation spacer and liner pattern configuration that reduces the horizontal area required for manufacturing and minimizes parasitic capacitance by forming an air tunnel and using a U-shaped liner pattern with an insulation pattern to cover the gate surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If contact plugs are positioned close to gates to reduce horizontal area, then area is reduced, but parasitic capacitance between contact plugs and gates increases
Solution Approach 1:
An insulation spacer is introduced as an intermediary element positioned between the contact plug and the gate. This spacer provides electrical isolation while allowing the contact plug to be positioned close to the gate, thereby reducing parasitic capacitance without increasing horizontal area. The spacer acts as a mediator that enables close positioning while maintaining electrical separation.
Solution Approach 2:
The gate structure is segmented into multiple components including the gate electrode, gate insulation layer, and side spacers. Additionally, the contact plug structure is segmented with a barrier layer and metal layer. This segmentation allows for optimized positioning and spacing, enabling the contact plug to be positioned close to the gate while maintaining proper electrical isolation through the various insulating layers.
2Object-generated harmful factors
If insulation spacer is added to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The insulation spacer is merged with the existing gate side spacers and interlayer insulation structures. The insulation spacer is formed as a continuous structure that integrates with the gate side spacers, eliminating the need for separate insulation elements. This merging approach reduces the number of discrete components while maintaining the parasitic capacitance reduction benefit.
Solution Approach 2:
The insulation spacer serves multiple functions: it provides electrical isolation between the contact plug and gate to reduce parasitic capacitance, it acts as a structural support element, and it serves as an etch stop layer during manufacturing. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
3Reliability
If second contact plug is added to contact gate electrode, then transistor performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The gate insulation layer and side spacers are formed in advance before the contact plug structures are created. The insulation spacer is preliminarily positioned between the contact plug and gate, establishing the electrical isolation framework before the contact plugs are formed. This preliminary action simplifies subsequent manufacturing steps by pre-establishing the isolation structure.
Solution Approach 2:
The insulation spacer automatically positions itself between the contact plug and gate through conformal deposition processes. The spacer forms conformally on the side walls of the gate and contact plug structures, self-adjusting to the exact positioning needed without requiring additional alignment steps. This self-positioning capability reduces manufacturing complexity while enabling the second contact plug to contact the gate electrode for enhanced transistor performance.
Data Source
AI summary
A semiconductor device includes gates extending in a first direction on a substrate, each gate of the gates including a gate insulation layer, a gate electrode, and a first spacer, first contact plugs contacting the substrate between adjacent ones of the gates, the first contact plugs being spaced apart from sidewalls of corresponding ones of the gates, a second contact plug contacting an upper surface of a corresponding gate electrode, the second contact plug being between first contact plugs, and an insulation spacer in a gap between the second contact plug and an adjacent first contact plug, the insulation spacer contacting sidewalls of the second contact plug and the adjacent first contact plug, and upper surfaces of the second contact plug and the adjacent first contact plug being substantially coplanar with each other.