Semiconductor Gate Electrode Contamination Control
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing semiconductor devices due to damage to interlayer dielectric layers and contamination of gate electrodes during the process of replacing dummy gate electrodes, which reduces yield and reliability.
Innovation Solution
An interface layer is formed over dummy gate structures and interlayer dielectric layers, which is harder to remove than the interlayer dielectric layer and has CMP selectivity with respect to gate electrodes, protecting the interlayer dielectric layer and preventing contamination from process byproducts and contaminants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gate electrodes are replaced with gate electrodes, then device functionality is improved, but interlayer dielectric layer damage and gate electrode contamination occur
Solution Approach 1:
A sacrificial layer is introduced as an intermediary between the interlayer dielectric layer and the gate electrode replacement process. This sacrificial layer absorbs the harmful effects of the replacement process, preventing damage to the interlayer dielectric layer and contamination of the gate electrodes while still enabling the functionality improvement of replacing dummy gate electrodes with actual gate electrodes.
Solution Approach 2:
The sacrificial layer is formed in advance before the gate electrode replacement process. This preliminary action prepares the structure to withstand the subsequent replacement process, ensuring that when dummy gate electrodes are removed and replaced with functional gate electrodes, the interlayer dielectric layer remains protected and clean without requiring additional cleaning or repair steps.
2Productivity
If conventional manufacturing processes are used, then production efficiency is maintained, but yield and reliability decrease due to contamination
Solution Approach 1:
The sacrificial layer serves as a mediator that prevents contamination during the gate electrode replacement process. By introducing this intermediate layer, the process maintains high production efficiency without the need for additional cleaning steps or rework, while simultaneously improving yield and reliability by preventing contaminant deposition on gate electrodes.
3Device complexity
If gate electrode replacement is performed without protection, then process complexity is reduced, but manufacturing precision deteriorates due to loss of control over gate structure height
Solution Approach 1:
The sacrificial layer acts as a precision-control intermediary during gate electrode replacement. It provides a controlled interface that enables precise control over gate structure height and positioning, preventing manufacturing defects while maintaining relatively simple process steps. The sacrificial layer's predetermined properties allow for controlled removal after gate electrodes are properly formed, ensuring high manufacturing precision.
Solution Approach 2:
The sacrificial layer enables controlled parameter changes during the replacement process. By adjusting the thickness, material composition, and removal conditions of the sacrificial layer, precise control over gate structure height and positioning is achieved. This parameter control ensures that gate electrodes are formed at the correct positions with accurate dimensions, improving manufacturing precision without significantly increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the control over gate structure height and prevents contamination, thereby improving the yield and reliability of semiconductor devices by protecting the interlayer dielectric layer during the replacement of dummy gate electrodes.
Implementation Method 1
the interface layer has a CMP selectivity with respect to the gate electrodes, such that the interface layer can protect the interlayer dielectric layer during the operation of replacing the dummy gate electrodes, and can prevent contaminants generated in an implant operation, a CMP operation and/or an etching operation from contaminating the gate electrodes
Implementation Method 2
A chemical mechanical polishing process is performed on the gate material layer to remove a portion of the gate material layer to form two gate electrodes in the cavities and expose the interface layer
Data Source
AI summary
A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.