Semiconductor Gate Electrode Formation Defect Prevention

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Solution Overview

Problem

The challenge in semiconductor device fabrication is the generation of defects, such as nodules, during the process of forming a gate electrode, which affects the quality and yield of high-integration, high-performance semiconductor devices.

Innovation Solution

A method involving the formation of a first and second growth-blocking layer on a temporary gate, using ion-implantation processes with specific angles and dopants like As, N, and C, to prevent defects by forming spacers and recessed regions, and subsequently removing these layers to expose the active region for gate electrode formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a temporary gate is formed crossing the active region, then the gate electrode formation process is enabled, but defects such as nodules are generated during the process

Engineering Contradiction:
Improvedefect preventionVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent divides the gate structure formation into multiple stages: first forming a temporary gate, then adding growth-blocking layers at specific locations, and finally removing the temporary gate to form the actual gate electrode. This segmentation allows defect prevention without requiring complete process redesign

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The growth-blocking layer acts as an intermediary element between the temporary gate and the active region. It prevents direct interaction that causes nodule formation while allowing the temporary gate to serve its function, and is later removed to complete the gate electrode formation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If growth-blocking layer is formed locally in the upper edge of the temporary gate, then nodule formation is prevented, but additional process steps are required

Engineering Contradiction:
Improvedefect controlVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The growth-blocking layer is applied locally only at the upper edge of the temporary gate where nodules form, rather than uniformly across the entire structure. This localized approach provides precise defect control while minimizing additional process complexity and material usage

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If the temporary gate is removed to expose the active region, then the gate electrode can be formed, but the active region must be precisely exposed without damage

Engineering Contradiction:
Improveactive region exposure precisionVSAvoidactive region damage
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The growth-blocking layer is formed in advance on the temporary gate before removal. This preliminary action protects the active region during the temporary gate removal process, preventing damage while enabling precise exposure of the active region for subsequent gate electrode formation

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces or prevents defect generation, improving the quality and yield of semiconductor devices by ensuring precise control over the gate electrode formation and reducing nodules.

Implementation Method 1

the forming of the first growth-blocking layer may include implanting dopants in the temporary gate, the temporary gate includes polysilicon, and the dopants include As, N, C, O, or a combination thereof

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9627207B2Methods of forming semiconductor device having gate electrode
Publication Date: 2017.04.18 SAMSUNG ELECTRONICS CO LTD
  • US9627207B2 patent drawing
  • US9627207B2 patent drawing
  • US9627207B2 patent drawing

AI summary

Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region.