Semiconductor Device Gate Dielectric Embedding
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Solution Overview
Problem
In high-voltage regions of semiconductor devices, the metal gate formed after chemical mechanical polishing (CMP) process is often lost due to protrusion of the gate dielectric layer from the substrate surface, leading to inferior device performance.
Innovation Solution
A method involving forming a doped region, a thermal oxide layer, and an epitaxial layer with a recess, followed by embedding a gate dielectric layer within the epitaxial layer to ensure coplanarity and protect the metal gate from CMP planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate dielectric layer on high-voltage region protrudes from the substrate surface, then the metal gate can be formed on the high-voltage region, but a large portion of the metal gate is lost by CMP process
Solution Approach 1:
An epitaxial layer is formed in advance on the substrate before forming the gate dielectric layer. This preliminary epitaxial layer structure provides a foundation that allows the gate dielectric layer to be formed at the same level as the surrounding substrate surface, preventing subsequent metal gate loss during CMP processing.
Solution Approach 2:
The gate dielectric layer is embedded within the epitaxial layer structure. The epitaxial layer acts as a container or matrix that holds the gate dielectric layer, ensuring that the gate dielectric layer does not protrude from the substrate surface and preventing metal gate loss during CMP.
2Manufacturing precision
If the gate dielectric layer is formed to be coplanar with the substrate surface, then metal gate loss is prevented, but the gate dielectric layer must be fully embedded requiring additional structural layers
Solution Approach 1:
The epitaxial layer serves multiple functions: it provides a structural foundation for forming the gate dielectric layer at the correct level, acts as an embedding matrix to prevent protrusion, and maintains surface coplanarity. This multi-functional approach achieves the desired coplanarity while managing the added structural complexity efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the metal gate on high-voltage regions from being lost during CMP, maintaining device performance by ensuring the gate dielectric layer is fully embedded and the surfaces are coplanar, thus enhancing the integrity and functionality of high-voltage semiconductor devices.
Implementation Method 1
forming a thermal oxide layer on the substrate and the doped region
Implementation Method 2
forming an epitaxial layer on the substrate and in the first recess
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a doped region in the substrate; forming a thermal oxide layer on the substrate and the doped region; removing the thermal oxide layer to form a first recess; forming an epitaxial layer on the substrate and in the first recess; and forming a gate dielectric layer in the epitaxial layer.