Semiconductor Gate Dielectric Fabrication via Sacrificial Layer Etching
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Solution Overview
Problem
Conventional semiconductor device fabrication methods face challenges in simultaneously forming high-voltage and low-voltage devices with appropriate gate dielectric layers, as existing processes are complex and do not allow for precise control of gate dielectric thickness, leading to inferior performance due to boron penetration and depletion effects.
Innovation Solution
A method is developed to fabricate semiconductor devices by defining regions for high-voltage and low-voltage transistors on a substrate, using sacrifice layers and etching steps to control the thickness of interfacial layers, allowing for precise formation of thicker gate dielectric layers for high-voltage devices and thinner layers for low-voltage devices, with sacrifice layers serving as etch stop layers during etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional poly-silicon gate is used, then the fabrication process is simple, but boron penetration and depletion effect occur which reduces gate capacitance and driving force
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional poly-silicon to metal gate materials (such as tungsten, titanium nitride, or tantalum nitride). This material substitution eliminates boron penetration and depletion effects while maintaining fabrication feasibility, thereby improving gate capacitance and driving force without significantly complicating the manufacturing process
Solution Approach 2:
The patent employs composite gate dielectric structures combining high-k dielectric materials (such as hafnium oxide, silicon oxide-nitride-oxide stacks) with metal gate electrodes. This composite structure achieves both high gate capacitance for improved driving force and compatibility with existing fabrication processes, resolving the contradiction between manufacturing simplicity and device performance
2Device complexity
If gate first process is used, then the process flow is simplified, but the gate dielectric layer thickness cannot be precisely controlled for different voltage requirements
Solution Approach 1:
The patent segments the gate dielectric formation process into separate stages: first forming a thick gate dielectric layer for high-voltage devices, then selectively removing portions to expose the substrate in specific regions, and finally forming a thin gate dielectric layer only where needed for low-voltage devices. This segmentation allows precise thickness control for different voltage requirements while maintaining a relatively simplified overall process flow
Solution Approach 2:
The patent performs preliminary formation of the thick gate dielectric layer across the entire substrate before selectively removing it in regions where low-voltage devices are to be formed. This preliminary action establishes the base structure that can be differentially processed, enabling precise thickness control without requiring completely separate fabrication lines for different voltage devices
3Manufacturing precision
If gate last process is used, then different gate dielectric thicknesses can be achieved, but the manufacturing process becomes complicated with sacrificial gates and multiple steps
Solution Approach 1:
The patent extracts and removes the sacrificial gate structure after it has served its purpose as a placeholder during fabrication. This extraction allows direct access to the substrate in specific regions for forming thin gate dielectric layers, achieving precise thickness differentiation without requiring the complex multi-step sacrificial gate processes of conventional gate-last methods
Solution Approach 2:
The patent performs preliminary formation of the thick gate dielectric layer across the entire substrate before selectively removing it in regions where low-voltage devices are to be formed. This preliminary action establishes the base structure that can be differentially processed, enabling precise thickness control without requiring completely separate fabrication lines for different voltage devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the precise control of gate dielectric thickness, improving the performance of semiconductor devices by allowing for the simultaneous formation of high-voltage and low-voltage transistors with optimized electrical properties.
Implementation Method 1
a first etching step is performed to remove the sacrifice gate layer in the first region and the second region. Then, a second etching step is performed to remove the sacrifice layer in the first region and the second region to expose the substrate of the second region
Data Source
AI summary
The present invention provides a method of fabricating a semiconductor device. A substrate is provided. A first region and a second region are defined on the substrate. A first interfacial layer, a sacrifice layer and a sacrifice gate layer are disposed on the first region. The sacrifice layer and the sacrifice gate layer are disposed on the second region of the substrate. Next, a first etching step is performed to remove the sacrifice gate layer in the first region and the second region. Then, a second etching step is performed to remove the sacrifice layer in the first region and the second region to expose the substrate of the second region. Lastly, a second interfacial layer is formed on the substrate of the second region.