Semiconductor Gate Dielectric Fabrication via Anti-Oxidation Masking
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Solution Overview
Problem
The existing methods for fabricating semiconductor devices with gate oxide layers of different thicknesses for high and low voltage transistors result in excessive recessing of the field oxide layer, leading to a lower device isolation breakdown voltage due to the etching process.
Innovation Solution
A method involving the formation of an anti-oxidation layer on a substrate with selective removal and thermal oxidization to create distinct gate oxide layers for high and low voltage regions, preventing excessive recessing and maintaining device isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick gate oxide layer is formed on the entire substrate and then etched in lower voltage regions to form thin gate oxide layers, then gate oxide layers with different thicknesses can be formed for high and low voltage transistors, but the field oxide layer is excessively recessed during etching, leading to lower device isolation breakdown voltage
Solution Approach 1:
The substrate is divided into high voltage device regions and low voltage device regions, with each region receiving different treatments. The field oxide layer is formed only in specific regions, and the gate oxide layer thickness is differentiated by region through selective formation processes, allowing precise control of oxide thickness in each segment without affecting other areas.
Solution Approach 2:
Different oxide layer configurations are applied to different regions of the substrate. High voltage regions receive thick gate oxide layers with field oxide layers for isolation, while low voltage regions receive thin gate oxide layers without field oxide layers. This local differentiation ensures each region has the optimal oxide structure for its voltage requirements while maintaining overall device reliability.
2Ease of manufacture
If the field oxide layer is recessed during the etching process to form thin gate oxide layers in lower voltage regions, then gate oxide thickness differentiation is achieved, but the device isolation breakdown voltage is reduced
Solution Approach 1:
The field oxide layer is formed in advance in high voltage regions before the gate oxide layer formation is completed. By预先 forming the field oxide layer with appropriate thickness and positioning, the subsequent gate oxide formation and etching processes can proceed without causing excessive recessing of the field oxide, thereby maintaining device isolation integrity while achieving the desired gate oxide thickness differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor devices with improved device isolation breakdown voltage and reduced process complexity by preventing excessive recessing of the field oxide layer, enabling the formation of gate oxide layers with precise thicknesses for both high and low voltage regions.
Implementation Method 1
selectively removing portions of the anti-oxidation layer on the substrate
Implementation Method 2
performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer
Data Source
AI summary
A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.