Semiconductor Device Gate Dielectric Formation via Nitride Treatment
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Solution Overview
Problem
Conventional semiconductor device fabrication methods face challenges in simultaneously forming high-voltage and low-voltage transistors with appropriate gate dielectric layers, as existing processes are complex and do not efficiently manage the thickness of these layers, leading to performance issues due to boron penetration and depletion effects.
Innovation Solution
A method is developed to form high-voltage and low-voltage transistors by creating a patterned mask layer and using a nitride treatment to remove residues without oxygen treatment, allowing the second spacer to maintain the trench width and enabling the formation of reliable devices with distinct gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If oxygen treatment is performed after exposing the second trench, then the mask layer residue is removed, but the second spacer is oxidized and removed, causing loss of trench width control
Solution Approach 1:
The patent extracts the harmful oxidation step from the process by replacing oxygen treatment with nitride treatment. This removes the source of the harmful effect (oxidation) while maintaining the beneficial function (residue removal). The nitride treatment selectively removes mask layer residue without oxidizing the second spacer, thus preserving trench width control.
Solution Approach 2:
The patent changes the chemical parameter of the treatment from oxidative (oxygen-based) to nitridative (nitride-based). This parameter change fundamentally alters the interaction with the second spacer: oxygen causes oxidation and removal, while nitride does not cause oxidation, thereby preventing the harmful effect while achieving the desired cleaning function.
2Adaptability or versatility
If conventional gate first or gate last processes are used, then metal gate is formed, but the process complexity increases and cannot simultaneously form high-voltage and low-voltage devices with different gate dielectric thicknesses
Solution Approach 1:
The patent segments the gate dielectric layer formation into two distinct regions: a first region with a first gate dielectric layer for high-voltage devices and a second region with a second gate dielectric layer for low-voltage devices. This segmentation allows each region to have optimized dielectric thickness independently, enabling simultaneous formation of both device types without requiring separate complex processing lines.
Solution Approach 2:
The patent applies local quality by providing different gate dielectric layer thicknesses in different spatial regions of the substrate. The first gate dielectric layer has a thickness suitable for high-voltage devices while the second gate dielectric layer has a thickness suitable for low-voltage devices. This local differentiation enables versatile device formation within a single unified process flow.
3Reliability
If poly-silicon gate is used, then conventional process is simple, but boron penetration and depletion effect occur, reducing gate capacitance and driving force
Solution Approach 1:
The patent changes the material parameter of the gate from poly-silicon to metal gate with high-k dielectric. This fundamental material parameter change eliminates the boron penetration and depletion effects that plague poly-silicon gates, thereby improving gate capacitance and driving force while maintaining process simplicity through the integrated formation approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the simultaneous fabrication of high-voltage and low-voltage transistors with controlled gate dielectric layers, improving device performance by maintaining trench width and preventing oxidation of the second spacer, thus enhancing the reliability and efficiency of the semiconductor device manufacturing process.
Implementation Method 1
a nitride treatment is performed to remove unwanted residue of the mask layer in the second recess
Data Source
AI summary
A method for forming a semiconductor device is provided. First, a dielectric layer is provided on a substrate, wherein a first recess and a second recess are formed in the dielectric layer. After a mask layer is filled into the first recess and the second recess, the mask layer in the second recess is removed away, thereby forming a patterned mask layer. Subsequently, a nitride treatment is performed to remove unwanted residue of the mask layer in the second recess.