Semiconductor Gate Dielectric Segmentation for Threshold Voltage Control
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Solution Overview
Problem
Current semiconductor fabrication methods are overly complex due to the need for precise control of threshold voltages and feature size reduction, particularly in high-k metal gate (HKMG) technology, which requires multiple patterning processes and etching steps to form different transistor types on the same chip.
Innovation Solution
A method involving the formation of sacrificial layers to act as etch masks for selectively removing work function layers, simplifying the process by eliminating the need for multiple photoresist and anti-reflection coating layers, and allowing for the formation of distinct work function layers and gate electrodes in different transistor regions without requiring extensive patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes and etching steps are used to form different transistor types on the same chip, then precise control of threshold voltages is achieved, but the fabrication process becomes overly complex
Solution Approach 1:
The patent divides the gate dielectric layer into different regions (first gate dielectric layer and second gate dielectric layer) with different dielectric constants. By segmenting the gate dielectric structure, the invention enables different threshold voltages for NMOS and PMOS transistors without requiring multiple patterning processes, thus reducing fabrication complexity while maintaining precise threshold voltage control.
Solution Approach 2:
The patent applies different dielectric materials with different dielectric constants to different regions of the gate dielectric layer. The first gate dielectric layer has a first dielectric constant while the second gate dielectric layer has a second dielectric constant different from the first. This local differentiation allows precise threshold voltage adjustment for different transistor types in different regions of the chip.
2Productivity
If feature size is reduced to arrange more transistors on a single chip, then transistor density increases, but fabrication challenges increase
Solution Approach 1:
By segmenting the gate dielectric layer into regions with different dielectric constants, the invention enables continued scaling to smaller feature sizes while maintaining the ability to form different transistor types. This segmentation approach simplifies the fabrication process at reduced dimensions compared to traditional multiple patterning methods.
3Manufacturing precision
If a work function layer is introduced to tune threshold voltage, then threshold voltage adjustment is achieved, but the formation process becomes more complicated
Solution Approach 1:
Instead of using a work function layer that requires complex patterning to achieve different threshold voltages, the patent directly incorporates different dielectric materials with different dielectric constants into the gate dielectric layer at specific locations. This local quality differentiation achieves threshold voltage tuning for different transistor types without the need for additional work function layer formation and patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the semiconductor fabrication process by reducing the number of patterning steps and enabling precise adjustment of threshold voltages across different transistor regions, enhancing the efficiency and accuracy of transistor formation.
Implementation Method 1
removing a portion of the first work function layer exposed by the first sacrificial layer using the first sacrificial layer as an etch mask
Data Source
AI summary
A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening.