Semiconductor Gate Dielectric Thickness Control via Selective Etching
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Solution Overview
Problem
Current semiconductor manufacturing processes for forming multiple gate dielectric layers with different thicknesses often affect the properties of field effect transistors (FETs), making it challenging to achieve desired threshold voltages and junction depths without compromising device performance.
Innovation Solution
A method involving the formation of isolation regions with insulating materials, sequential deposition and removal of dielectric layers, and precise masking to create FETs with distinct gate dielectric thicknesses, allowing for the fabrication of FETs with varying threshold voltages and uniform source-drain junction depths without affecting device properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple gate dielectric layers are formed with different thicknesses using conventional processes, then FETs with different threshold voltages can be achieved, but the device properties and performance are adversely affected
Solution Approach 1:
The gate dielectric layer is segmented into multiple regions with different thicknesses within the same continuous layer structure. This is achieved by performing selective removal (etching) of the gate dielectric layer in specific regions after uniform formation, creating thin and thick regions that enable different threshold voltages for NFET and PFET while maintaining overall device performance through the continuous layer architecture.
2Adaptability or versatility
If gate dielectric layers are selectively removed to create different thicknesses, then FET properties can be adjusted, but the manufacturing process complexity increases
Solution Approach 1:
A protective layer is formed preliminarily over specific regions of the gate dielectric layer before the selective removal process. This preliminary protective layer formation simplifies the subsequent etching process by defining the regions that should retain their original thickness, thereby reducing the overall process complexity while achieving the desired differential thickness structure.
Solution Approach 2:
The protective layer acts as an intermediary element that facilitates the selective removal process. It is formed over regions where the gate dielectric layer should be preserved, allowing the etching process to selectively remove the gate dielectric only in regions not covered by the protective layer, thus simplifying the control of differential thickness without requiring complex masking and alignment processes.
3Adaptability or versatility
If conventional multiple gate dielectric formation processes are used, then different threshold voltages can be achieved, but source-drain junction depth uniformity is compromised
Solution Approach 1:
The gate dielectric layer is segmented into regions of different thicknesses through selective removal after uniform formation, allowing NFET and PFET to have different threshold voltages. This segmentation approach maintains uniform source-drain junction depths because the segmentation occurs in the gate dielectric layer itself rather than affecting the underlying substrate or source-drain regions, thereby decoupling threshold voltage control from junction depth control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of FETs with controlled gate dielectric thicknesses, ensuring consistent performance and threshold voltages while maintaining the integrity of FET properties, facilitating the production of devices like embedded flash memory and high-voltage FETs.
Implementation Method 1
A first silicon oxide layer is formed by thermal oxidation
Data Source
AI summary
In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.