Semiconductor Gate Structures Using Dipole Layers for Threshold Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving multi-functional FETs with ultra-low and different threshold voltages while maintaining cost-effectiveness and efficiency, particularly in the scaling down of devices like GAA FETs, finFETs, and MOSFETs, where depositing different work function metal layer thicknesses becomes increasingly challenging.
Innovation Solution
The method involves forming NFETs and PFETs with similar work function metal layer thicknesses but different threshold voltages on the same substrate by doping high-K gate dielectric layers with metallic dopants to induce dipoles of varying polarities and concentrations, and using dual metal oxide layers to adjust effective work function values without varying the work function metal layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different work function metal layer thicknesses are deposited to achieve different threshold voltages, then FETs with different threshold voltages can be formed, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent applies local quality by doping the gate dielectric layer with metallic dopants at specific locations and concentrations to create different threshold voltages in different FET regions. Instead of varying the work function metal layer thickness across the entire structure, the dopants are selectively introduced into the gate dielectric layer of specific FETs (e.g., NFETs vs PFETs) to achieve the desired threshold voltage differentiation. This localized modification simplifies the manufacturing process while maintaining the ability to produce FETs with different threshold voltages.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate dielectric layer by introducing metallic dopants with varying concentrations and types (e.g., different metal elements). By adjusting the dopant concentration and species, the effective work function of the gate dielectric is modified, which directly controls the threshold voltage of the FET. This parameter change approach allows for threshold voltage tuning without requiring different metal layer thicknesses, thereby reducing manufacturing complexity.
2Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then higher performance is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses dimensional scaling challenges by changing the electrical parameters (threshold voltage) through chemical doping rather than relying solely on precise dimensional control. As device dimensions are reduced, the dopant concentration in the gate dielectric can be adjusted to compensate for scaling effects and maintain the desired threshold voltage characteristics. This approach reduces the stringency of dimensional control requirements while preserving device performance.
3Ease of manufacture
If manufacturing processes are simplified to reduce costs, then production efficiency improves, but the ability to produce FETs with different threshold voltages may be compromised
Solution Approach 1:
The patent makes the gate dielectric layer multi-functional by using it both as the insulating barrier and as a means to control threshold voltage through metallic dopant incorporation. This universal approach allows a single gate dielectric layer to serve dual purposes: electrical isolation and threshold voltage tuning. Consequently, the manufacturing process is simplified as it requires only one doping step rather than multiple steps involving different metal layers with varying thicknesses, thereby maintaining cost-effectiveness while preserving threshold voltage differentiation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of FETs with ultra-low and different threshold voltages, reducing manufacturing costs by 20-30% and time by 15-20%, while allowing for smaller gate stack dimensions and improved electrical isolation.
Implementation Method 1
The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor the first dielectric layer.
Data Source
AI summary
A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.