Semiconductor Gate Structure with Fluorinated Dipole Layer for Leakage Control
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in managing threshold voltage, interface trap density, reliability, and gate leakage.
Innovation Solution
Formation of a dipole layer comprising metal atoms over an interfacial layer, followed by a fluorine incorporation process and anneal to drive metal and fluorine atoms into the interfacial layer, improving the threshold voltage and reducing gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but threshold voltage control, interface trap density, reliability, and gate leakage become more difficult to manage
Solution Approach 1:
A dipole layer comprising metal atoms is formed over the interfacial layer before final gate dielectric deposition. This preliminary action of creating the dipole layer enables subsequent fluorine incorporation and annealing processes that drive metal and fluorine atoms into the interfacial layer, thereby improving threshold voltage and reducing gate leakage before the device is fully operational
Solution Approach 2:
The patent employs fluorine incorporation into the dipole layer and subsequent annealing to drive metal and fluorine atoms into the interfacial layer. This changes the chemical and physical parameters of the interfacial layer, improving its quality and enabling better threshold voltage control and reduced gate leakage in scaled devices
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but interface trap density increases
Solution Approach 1:
The dipole layer is formed in advance over the interfacial layer, creating a structure that enables subsequent fluorine incorporation and annealing processes. This preliminary structure preparation allows for effective reduction of interface trap density through controlled atomic diffusion into the interfacial layer
Solution Approach 2:
Fluorine incorporation and annealing processes modify the interfacial layer parameters by driving metal and fluorine atoms into it. These parameter changes improve the interface quality and reduce interface trap density, addressing the harmful effects of device scaling
3Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but gate leakage increases
Solution Approach 1:
The dipole layer comprising metal atoms is formed before final gate dielectric deposition, creating a structure that enables subsequent fluorine incorporation. This preliminary action sets up the conditions for driving metal and fluorine atoms into the interfacial layer, which effectively reduces gate leakage in scaled devices
Solution Approach 2:
The annealing process drives metal and fluorine atoms into the interfacial layer, changing its electrical and physical parameters. These parameter changes improve the gate stack quality and reduce gate leakage, enabling continued device scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances threshold voltage, improves reliability, and reduces or eliminates gate leakage in semiconductor devices.
Implementation Method 1
Formation of a dipole layer comprising metal atoms over an interfacial layer
Implementation Method 2
followed by a fluorine incorporation process
Implementation Method 3
anneal to drive metal and fluorine atoms into the interfacial layer
Implementation Method 4
anneal to drive metal and fluorine atoms into the interfacial layer
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interfacial layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interfacial layer. The dipole layer includes metal atoms. Fluorine atoms are incorporated in the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interfacial layer. The dipole layer is removed.