Semiconductor Gate Drive Circuit With Three-Level Switching Control

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Solution Overview

Problem

Existing drive devices for semiconductor devices, such as IGBTs, face challenges in minimizing loss during turn-on and turn-off operations due to inefficiencies in electron injection and carrier accumulation rates.

Innovation Solution

A drive device with a drive circuit that supplies a three-level drive signal to the control gate electrode, allowing for faster electron injection and carrier accumulation, thereby reducing turn-on and turn-off losses by optimizing the voltage and current changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a traditional two-level drive signal is used to drive the semiconductor device, then the device can be operated with a simple drive circuit, but the electron injection and carrier accumulation rates are insufficient, resulting in higher turn-on and turn-off losses

Engineering Contradiction:
Improveturn-on loss and turn-off lossVSAvoiddrive signal configuration
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The gate drive signal is segmented into three distinct levels (first potential, second potential higher than first, and third potential between first and second) applied to different gate electrodes (third and fourth electrodes). This segmentation allows independent control of electron injection and carrier accumulation processes, optimizing both turn-on and turn-off characteristics separately to reduce energy losses.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The drive signal parameters are changed from a simple two-level configuration to a three-level configuration with specifically optimized potentials. The first potential is set to inject electrons, the second potential accumulates carriers, and the third potential controls the turn-off process. This parameter optimization reduces turn-on loss by 50% and turn-off loss by 37% compared to traditional configurations.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If a three-level drive signal is supplied to the control gate electrode, then electron injection and carrier accumulation rates increase, but the drive circuit complexity increases

Engineering Contradiction:
Improveelectron injection rate and carrier accumulation rateVSAvoiddrive signal configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The gate drive signal is segmented into three distinct levels (first potential, second potential higher than first, and third potential between first and second) applied to different gate electrodes (third and fourth electrodes). This segmentation allows independent control of electron injection and carrier accumulation processes, optimizing both turn-on and turn-off characteristics separately to reduce energy losses.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The drive circuit is configured to supply the three-level drive signal in a specific sequence: first potential to initiate electron injection, then second potential to accumulate carriers before switching, and finally third potential to control turn-off. This preliminary arrangement of signal levels optimizes the timing and efficiency of electron injection and carrier accumulation, achieving 50% reduction in turn-on loss and 37% reduction in turn-off loss.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11923851B2Drive device and semiconductor module
Publication Date: 2024.03.05 KK TOSHIBA
  • US11923851B2 patent drawing
  • US11923851B2 patent drawing
  • US11923851B2 patent drawing

AI summary

According to one embodiment, a drive device includes a drive circuit configured to drive a semiconductor device. The semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to fourth semiconductor region. The first semiconductor region includes first to third partial regions. The first semiconductor region is between the first electrode and the second semiconductor region. The third semiconductor region is between the first and second semiconductor regions. The fourth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The first partial region is between the fourth semiconductor region and the third electrode. The second partial region is between the fourth semiconductor region and the fourth electrode. A part of the insulating member is provided between the semiconductor member and the third and fourth electrodes.