Semiconductor Gate Driver Circuit for Low-Distortion Signal Timing
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Solution Overview
Problem
Existing semiconductor devices with gate driver circuits experience signal delay or distortion, transistor deterioration, and prolonged rise or fall times in gate signal lines due to the structure of separate gate driver circuits on either side of the pixel portion.
Innovation Solution
A semiconductor device design where both gate driver circuits output selection signals during selection periods and one outputs non-selection signals during non-selection periods, with one circuit turning off during non-selection to reduce signal delay and transistor deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both gate driver circuits output signals during selection periods and one outputs non-selection signals during non-selection periods, then signal delay and distortion are reduced, but device complexity increases
Solution Approach 1:
The gate driver circuit is divided into two separate gate driver circuits (first and second) that independently control different sets of gate lines. Each circuit operates semi-independently, with the first circuit controlling odd-numbered gate lines and the second circuit controlling even-numbered gate lines, allowing parallel operation during selection periods and reduced activity during non-selection periods.
Solution Approach 2:
The gate driver circuits operate in periodic cycles of selection periods and non-selection periods. During selection periods, both circuits actively output signals to drive gate lines. During non-selection periods, one circuit is turned off while the other maintains operation, creating a periodic on/off pattern that reduces overall circuit activity and signal interference.
2Reliability
If one gate driver circuit turns off during non-selection periods, then transistor deterioration is suppressed, but signal output capability is reduced
Solution Approach 1:
The gate driver circuit is segmented into two independent circuits that can operate separately. This allows one circuit to be turned off during non-selection periods to reduce transistor stress and deterioration, while the other circuit remains active to maintain signal output capability when needed.
Solution Approach 2:
The circuits operate in periodic cycles where one circuit is activated during selection periods and deactivated during non-selection periods. This periodic on/off operation reduces cumulative transistor deterioration while ensuring signal output capability is maintained through the alternating operation of the two circuits.
3Speed
If both gate driver circuits output signals during selection periods, then rise and fall times are shortened, but power consumption increases
Solution Approach 1:
Both gate driver circuits are merged to operate simultaneously during selection periods, combining their output capabilities to drive gate lines with faster rise and fall times. This parallel operation achieves high-speed signal transitions while maintaining coordinated control of the display panel.
Solution Approach 2:
The circuits operate in periodic cycles where both are active during selection periods for high-speed operation, and one is deactivated during non-selection periods to reduce power consumption. This periodic activation pattern balances speed requirements with energy efficiency.
Data Source
AI summary
A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.