Semiconductor Gate Fabrication with Dual Mask Hard Mask Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device fabrication methods face issues such as leakage current due to tunneling effects and inferior performance caused by boron penetration and depletion effects, especially when using high-K gate dielectric layers and metal gates, which require improved methods for superior performance and reliability.
Innovation Solution
A method involving two mask layers is used to sequentially remove hard masks from gate structures, where a first mask layer is formed and partially removed to expose the second hard mask, followed by complete removal of the second hard mask, and then a second mask layer is formed and partially removed to expose and completely remove the first hard mask, ensuring precise control and protection of substrate devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon dioxide or silicon oxynitride gate dielectric layer is used, then manufacturing process is simple, but leakage current occurs due to tunneling effect and physical limit thickness is reached
Solution Approach 1:
The gate dielectric layer is segmented into multiple layers: a first gate dielectric layer (conventional silicon dioxide or silicon oxynitride) and a second gate dielectric layer (high-K material). This segmentation allows the lower layer to provide good interface characteristics while the upper layer reduces leakage current through tunneling, thus improving reliability without requiring a complete structural overhaul.
Solution Approach 2:
The patent uses composite gate dielectric structure combining conventional dielectric materials (silicon dioxide, silicon oxynitride) with high-K materials. This composite approach leverages the advantages of both material types: the conventional materials provide stable interfaces while the high-K material provides superior electrical insulation properties, reducing leakage current effectively.
2Reliability
If conventional polysilicon gate is used, then manufacturing process is simple, but performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The gate structure is segmented into multiple components: a gate electrode (metal or polysilicon), a gate dielectric layer, and hard masks. This segmentation allows the gate electrode to be optimized for electrical performance while the gate dielectric and hard masks are optimized for manufacturing and protection functions, thereby improving device performance without excessive complexity.
Solution Approach 2:
The patent introduces work function metals as intermediary materials between the gate electrode and the gate dielectric. These intermediary layers (such as titanium nitride, tantalum nitride) serve to adjust the work function and prevent direct contact between the metal gate and high-K dielectric, preventing contamination while maintaining electrical performance.
3Productivity
If single mask layer is used to remove hard masks, then process steps are reduced, but shallow trench isolation structures may be damaged
Solution Approach 1:
The mask removal process is segmented into two distinct stages: first removing the second hard mask using a first mask layer, then removing the first hard mask using a second mask layer. This segmentation allows selective protection of shallow trench isolation structures during each removal step, preventing damage while maintaining reasonable process efficiency.
Solution Approach 2:
The patent applies preliminary protective actions by forming specific mask layers before each hard mask removal step. The first mask layer is formed and patterned to protect shallow trench isolation structures during second hard mask removal, and the second mask layer is formed and patterned to protect during first hard mask removal. These preliminary protective measures prevent damage before it can occur.
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a gate structure on the first region, in which the gate structure comprises a first hard mask and a second hard mask thereon; forming a first mask layer on the first region and the second region; removing part of the first mask layer; removing the second hard mask; forming a second mask layer on the first region and the second region; removing part of the second mask layer; and removing the first hard mask.