Semiconductor Device Gate Electrode dV/dt Control
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Solution Overview
Problem
Conventional insulated gate bipolar transistors (IGBTs) face challenges in controlling the rate of voltage change over time (dV/dt) during turn-on, which affects electro-magnetic compatibility and increases turn-on loss, particularly due to the displacement current flowing through the floating p+-type region.
Innovation Solution
The semiconductor device incorporates a trench gate-type MOS gate structure with a second gate electrode partially covering the floating p+-type region, increasing the Cgp/Csp ratio to reduce the maximum dV/dt and improve turn-on dV/dt controllability without increasing the gate resistance Rg, by forming a semiconductor device with specific layer configurations and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate resistance Rg is increased to reduce dV/dt, then turn-on dV/dt controllability is improved, but turn-on loss increases and turn-on speed decreases
Solution Approach 1:
The patent introduces a floating p+-type region as an intermediary element between the n- type drift layer and the p-type base region. This floating region acts as a mediator to control the displacement current path during turn-on, enabling dV/dt controllability without relying on increased gate resistance, thus avoiding the associated turn-on loss and speed degradation
Solution Approach 2:
The patent changes the electrical parameters of the device by introducing a floating p+-type region with specific impurity concentration and geometric dimensions. This parameter change modifies the displacement current characteristics and capacitance ratios (Cgp/Csp), enabling improved dV/dt controllability through structural parameters rather than resistance changes
2Reliability
If gate resistance Rg is increased to reduce dV/dt, then turn-on dV/dt controllability is improved, but turn-on speed decreases
Solution Approach 1:
The floating p+-type region serves as an intermediary structure that controls the displacement current flow during turn-on. By providing an alternative current path through this floating region, the patent achieves dV/dt controllability without slowing down the overall turn-on speed, as the gate resistance does not need to be increased
3Ease of manufacture
If conventional trench gate structure is used, then manufacturing is simplified, but turn-on dV/dt controllability degrades due to displacement current through floating p+-type region
Solution Approach 1:
The patent segments the device structure by dividing the active region into distinct zones: the n- type drift layer, the floating p+-type region, and the p-type base region. This segmentation allows independent optimization of each region's function, enabling improved dV/dt controllability through the floating region while maintaining the simple trench gate manufacturing structure
Solution Approach 2:
The patent modifies the structural parameters of the floating p+-type region (impurity concentration, depth, width) to optimize the Cgp/Csp capacitance ratio. This parameter optimization enables improved turn-on dV/dt controllability while maintaining compatibility with conventional trench gate manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration suppresses Miller capacitance increases, enhances the Cgp/Csp ratio, and reduces turn-on dV/dt, thereby improving turn-on dV/dt controllability and preventing increased turn-on loss without increasing gate resistance, and simplifies the manufacturing process by eliminating the need for an emitter trench.
Implementation Method 1
Cgp/Csp>2.0 is satisfied, where Cgp is electrostatic capacitance between the third semiconductor region and the first and second gate electrodes and Csp is electrostatic capacitance between the third semiconductor region and the first electrode
Data Source
AI summary
In mesa regions between adjacent trenches disposed in an n−-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.