Semiconductor Gate Electrode with Etch-Selective Barrier Patterns

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Solution Overview

Problem

The process of replacing nitride layers with conductive layers in 3-dimensional nonvolatile memory devices is challenging, as reactive gases can damage surrounding layers, degrading the memory device characteristics.

Innovation Solution

A semiconductor device structure and manufacturing method involving conductive layers with specific barrier patterns and material patterns, allowing for etch selectivity, and the use of insulating layers alternately stacked with conductive layers, which helps in forming a gate electrode with a dielectric layer between the channel layer and the gate electrode, preventing damage from reactive gases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If nitride layers are replaced with conductive layers in the manufacturing process, then the gate electrode structure is formed, but reactive gases damage surrounding layers degrading device characteristics

Engineering Contradiction:
Improvegate electrode formation processVSAvoidmemory device characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An intermediate layer is introduced between the nitride layer and the conductive layer. This intermediate layer serves as a protective barrier that prevents reactive gases from the conductive layer deposition process from damaging the surrounding oxide layers and nitride layers, while still allowing the gate electrode structure to be formed. The intermediate layer is selectively removed later in the process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The intermediate layer is formed in advance before the conductive layer is deposited. This preliminary action prepares the structure to withstand the harmful effects of reactive gases during subsequent deposition processes, protecting the surrounding layers before damage can occur.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the process of replacing nitride layers with conductive layers is performed, then the gate electrode is formed, but the surrounding layers are damaged by remaining reactive gases

Engineering Contradiction:
Improvegate electrode structureVSAvoidreactive gas damage to surrounding layers
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The intermediate layer acts as a mediator that shields the surrounding oxide and nitride layers from the harmful reactive gases released during conductive layer deposition. This protective barrier allows the complex gate electrode structure to be formed without compromising the integrity of adjacent layers.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The intermediate layer provides beforehand cushioning or protection to the surrounding layers against the harmful effects of reactive gases. By placing this protective layer in advance, the structure is cushioned against damage before the deposition process begins.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the characteristics of the memory device by simplifying the manufacturing process and preventing damage to surrounding layers, thereby improving the device's performance and integration.

Implementation Method 1

a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern

Methodology Applied
Scientific EffectEtch selectivity:

Data Source

PatentUS9418892B2Transistor, semiconductor device and method of manufacturing the same
Publication Date: 2016.08.16 SK HYNIX INC
  • US9418892B2 patent drawing
  • US9418892B2 patent drawing
  • US9418892B2 patent drawing

AI summary

A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.