Semiconductor Gate Electrode Curvature Mitigates Field Concentration
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Solution Overview
Problem
Semiconductor devices, particularly IGBTs, face reliability issues due to frequent breakdown of the gate insulation layer, especially with a large number of gate electrodes, leading to reduced operational efficiency and increased electric field concentration at the ends of electrode portions.
Innovation Solution
The semiconductor device configuration includes gate electrodes with connected first and second electrode portions extending in one direction and connected third and fourth electrode portions that mitigate electric field concentration by reducing the likelihood of breakdown through the use of plugs that connect the gate electrodes to the gate pad without pulling up the curved portions, and gentle curvature designs for the third and fourth electrode portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of gate electrodes is increased to improve device functionality, then the device can handle higher power or current, but the gate insulation layer becomes more prone to breakdown due to increased electric field concentration
Solution Approach 1:
The gate electrode is divided into multiple gate electrode portions (first, second, third, fourth portions) arranged in a specific pattern. This segmentation distributes the electric field more evenly across the gate insulation layer, preventing concentration at single points and reducing breakdown risk while maintaining high power handling capability through the multi-portion structure
Solution Approach 2:
An intermediate insulating layer is introduced between the gate electrode portions and the semiconductor regions. This intermediary layer helps distribute and mitigate the electric field, acting as a buffer that prevents direct concentration of high electric fields at the gate insulation layer, thereby improving reliability without sacrificing power capability
2Ease of manufacture
If the gate electrode portions are pulled up to reduce curvature, then manufacturing becomes easier, but electric field concentration increases at the ends of electrode portions
Solution Approach 1:
The gate electrode portions are designed with gentle curvature rather than sharp angles or straight edges. This curved geometry naturally distributes the electric field more evenly along the electrode portions, preventing concentration at ends or corners. The gentle curvature maintains manufacturing feasibility while significantly improving electric field distribution and reducing breakdown risk
3Productivity
If the gap between gate electrode portions is narrowed to increase device density, then more gate electrodes can be packed in the same area, but the gate insulation layer becomes more susceptible to breakdown
Solution Approach 1:
The design implements different characteristics at different locations: the gate electrode portions have gentle curvature at critical areas to distribute electric fields, while the gaps between portions are optimized for density. The intermediate insulating layer provides enhanced insulation specifically in the high-stress regions between closely spaced portions, allowing narrow gaps without compromising reliability
Data Source
AI summary
A semiconductor device includes a plurality of gate electrodes. Each gate electrode includes a first portion extending from a first end to a second end and a second portion extending parallel the first portion from a first end to a second end. The first and second portions are spaced from each other. A third portion of at least one gate electrode connects the first end of the first portion to the first end of the second portion of the gate electrode. A first insulating film is on the plurality of gate electrodes. A first interconnect portion is disposed on the first or second portion the gate electrode to electrically connecting the gate electrode to a gate pad. A second interconnect portion is disposed on semiconductor regions between the gate electrodes and electrically connects the semiconductor regions to an emitter pad.