Semiconductor Device Gate Electrode Formation Method
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Solution Overview
Problem
The manufacturing method of semiconductor devices, particularly RAM, faces alignment issues due to shrinking word line spacing and multiple photolithography processes, leading to potential short circuits and challenges in forming RAM with smaller pitches.
Innovation Solution
A novel manufacturing method where the gate electrode is formed first, followed by the word line and bit line, reducing the number of photolithography processes and improving alignment, with the use of a seed layer, conductive layer, and gate dielectric layers to create a semiconductor device structure that enhances reliability and allows for smaller pitch formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple photolithography processes are used to form gate electrode and word line, then the semiconductor device can be manufactured with conventional processes, but alignment problems occur and short circuits may be generated
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by forming the gate electrode first through selective epitaxial growth, and then forming the word line and bit line subsequently. This reversal of the traditional process sequence eliminates alignment issues between gate electrode and word line that occur in conventional photolithography-based manufacturing, while still maintaining ease of manufacture through established semiconductor processing techniques.
Solution Approach 2:
The gate electrode is formed in advance before the word line and bit line are created. This preliminary formation of the gate electrode structure allows subsequent layers to be deposited and patterned without alignment concerns, as the gate electrode serves as a pre-established reference structure that eliminates the need for precise photolithographic alignment between gate and word line.
2Productivity
If word line spacing is reduced to achieve smaller pitch RAM, then the integration density increases, but alignment problems worsen and reliability decreases
Solution Approach 1:
By inverting the manufacturing sequence to form the gate electrode first, the patent enables reduced word line spacing without compromising reliability. The gate electrode is established as a stable reference structure before subsequent patterning steps, eliminating alignment errors that would otherwise worsen with smaller pitches and ensuring reliable device operation at higher integration densities.
3Ease of manufacture
If conventional photolithography process is used, then the manufacturing process is straightforward, but the number of photolithography steps increases leading to alignment errors
Solution Approach 1:
The patent extracts the gate electrode formation step from the conventional photolithography sequence and implements it through selective epitaxial growth. This removes the need for photolithography steps specifically for gate electrode patterning, reducing the total number of photolithography processes while maintaining ease of manufacture through other established semiconductor fabrication techniques.
Solution Approach 2:
The patent replaces the photolithography-based mechanical patterning system with selective epitaxial growth for gate electrode formation. This substitution eliminates the alignment constraints inherent in photolithography while maintaining process simplicity, as epitaxial growth is a well-established semiconductor manufacturing technique that can be precisely controlled without requiring complex photolithographic alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the likelihood of short circuits and enables the production of RAM with smaller pitches by minimizing photolithography steps, improving the reliability and performance of semiconductor devices.
Implementation Method 1
a seed layer is formed to cover an upper surface of the first source/drain layer, a sidewall of the first hole, and an upper surface of the dielectric layer
Implementation Method 2
the patterned gate electrode is formed by a plating deposition
Implementation Method 3
the conductive layer is formed by a plating deposition
Data Source
AI summary
The semiconductor device includes a first source/drain layer, a dielectric layer, a channel, a gate electrode, a first gate dielectric layer, a seed layer, a conductive layer, and a second source/drain layer. The dielectric layer is disposed on the first source/drain layer, in which the dielectric layer has a hole penetrating the dielectric layer. The channel is disposed in the hole and extends substantially perpendicular to an upper surface of the first source/drain layer. The gate electrode surrounds the channel. The first gate dielectric layer is disposed between the gate electrode and the channel. The seed layer is disposed between the gate electrode and the dielectric layer and on an upper surface of the dielectric layer, in which the seed layer covers a portion of a sidewall of the hole.