Semiconductor Gate Electrode Hybridization for Speed and Reliability

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Solution Overview

Problem

Semiconductor devices face challenges in balancing the need for stability and fast operating speed, as silicon gate electrodes provide reliability but slower speeds, while metal gate electrodes offer faster speeds but lower processing reliability.

Innovation Solution

A semiconductor device is fabricated using a silicon electrode for stable operations and a metal electrode for high-speed operations, with a method involving forming gate patterns and silicide layers on a substrate, where the first gate insulating layer is thicker than the second, and the second gate insulating layer includes a chemical silicon oxide and high-k layer, to optimize transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a silicon gate electrode is used, then reliability is improved, but operating speed deteriorates

Engineering Contradiction:
Improveprocessing reliabilityVSAvoidoperating speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies different gate electrode materials to different active areas: silicon gate electrodes are used in first active areas where reliability is prioritized, while metal gate electrodes are used in second active areas where fast operating speed is required. This local differentiation resolves the contradiction by allowing each region to optimize for its specific performance requirement.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The semiconductor device is segmented into multiple active areas with different gate electrode configurations. The substrate is divided into first active areas (with silicon gates) and second active areas (with metal gates), allowing independent optimization of reliability and speed in different segments of the same device.

Inventive Principle:
Principle #1Segmentation

2Speed

If a metal gate electrode is used, then operating speed is improved, but reliability deteriorates

Engineering Contradiction:
Improveoperating speedVSAvoidprocessing reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

Metal gate electrodes are selectively applied only to second active areas where fast operating speed is the primary requirement. This localized application allows the device to achieve high speed performance in specific regions without compromising the overall reliability of the semiconductor device.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The device structure is segmented to separate metal gate regions from silicon gate regions, allowing metal gates to provide high-speed performance in designated areas while silicon gates maintain reliability in other areas, thus resolving the trade-off between speed and reliability.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If different gate insulating layer thicknesses are used, then transistor performance is optimized, but manufacturing complexity increases

Engineering Contradiction:
Improvetransistor performance optimizationVSAvoidgate structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Different thicknesses of gate insulating layers are applied to different active areas: a first gate insulating layer with a first thickness is formed for first active areas, and a second gate insulating layer with a second thickness is formed for second active areas. This allows optimization of transistor performance for different device types while managing manufacturing complexity through selective application.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9059090B2Semiconductor device and method for fabricating the same
Publication Date: 2015.06.16 SAMSUNG ELECTRONICS CO LTD
  • US9059090B2 patent drawing
  • US9059090B2 patent drawing
  • US9059090B2 patent drawing

AI summary

A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.