Semiconductor Gate Electrode Layer Structures for Multi-Voltage Transistors
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Solution Overview
Problem
The increasing demand for high-performance, high-speed semiconductor devices with higher integration levels poses challenges in scaling down transistors while maintaining optimal operating characteristics, particularly in planar metal oxide semiconductor FETs, leading to the need for innovative structures like FinFETs with varied operating voltages.
Innovation Solution
The semiconductor device incorporates a substrate with multiple regions, each with distinct gate electrode layers having different conductive layers and thicknesses, work functions, and shapes, allowing for transistors with the same channel lengths but different operating voltages by adjusting the structure of gate electrode layers and dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased, then productivity and performance are improved, but transistor size must be scaled down which deteriorates manufacturing precision and operating characteristics
Solution Approach 1:
The patent applies local quality by forming different gate electrode layer structures in different regions of the semiconductor device. First gate electrode layers with uniform thickness are formed in first regions, while second gate electrode layers with non-uniform thickness (thicker at edges, thinner at center) are formed in second regions. This allows each region to have optimized electrical characteristics suitable for its specific function, enabling high integration without compromising manufacturing precision.
Solution Approach 2:
The gate electrode layers are segmented into multiple types (first gate electrode layers and second gate electrode layers) with different structural characteristics. This segmentation allows independent optimization of different transistor regions, enabling the device to achieve high integration density while maintaining precise control over each segment's electrical properties.
2Productivity
If transistor size is scaled down, then integration density is improved, but operating characteristics deteriorate due to reduced control over channel current
Solution Approach 1:
Different gate electrode structures are implemented in different regions to locally optimize operating characteristics. The second gate electrode layers with non-uniform thickness provide enhanced edge effects that improve channel control in specific regions, compensating for the reduced control authority that normally occurs with scaled-down transistor dimensions.
Solution Approach 2:
The patent introduces thickness variation as an additional dimensional parameter for gate electrode layers. By controlling the thickness profile (uniform vs. non-uniform) in the vertical dimension, the invention achieves improved channel control without further reducing the horizontal transistor dimensions, thus maintaining operating characteristics while preserving integration density.
3Ease of manufacture
If all transistors have the same gate electrode layer structure, then manufacturing simplicity is maintained, but versatility in operating voltages and threshold voltages is limited
Solution Approach 1:
The patent implements local quality by creating different gate electrode layer structures (first and second types) in different regions. The second gate electrode layers with non-uniform thickness provide enhanced edge effects that enable independent control of threshold voltages and operating characteristics for transistors in different regions, achieving multi-voltage operation while maintaining a relatively simple manufacturing process.
4Manufacturing precision
If gate electrode layers have uniform thickness, then manufacturing precision is simplified, but ability to control threshold voltage and operating characteristics is reduced
Solution Approach 1:
The invention applies local quality by forming second gate electrode layers with non-uniform thickness profiles in specific regions. These layers are thicker at the edge portions and thinner at the center portion, creating localized electric field enhancements at the edges. This allows precise control of threshold voltages and operating characteristics for transistors in different regions without compromising overall manufacturing precision.
Data Source
AI summary
A semiconductor device includes a substrate having first and second regions, a first gate electrode layer on the first region, and including a first conductive layer, and a second gate electrode layer on the second region, and including the first conductive layer, a second conductive layer on the first conductive layer, and a barrier metal layer on the second conductive layer, wherein an upper surface of the first gate electrode layer is at a lower level than an upper surface of the second gate electrode layer.