Semiconductor Device Gate Electrode Structure for Switching Noise Reduction
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Solution Overview
Problem
The downsizing of power supply circuits, such as switching power supplies, leads to increased switching frequency, resulting in higher switching losses and reduced efficiency due to increased gate-drain capacitance resonance, causing high-frequency noise and reduced gate controllability.
Innovation Solution
A semiconductor device structure with a gate electrode provided under the gate pad electrode, incorporating a high internal gate resistance and adjusted gate-drain capacitance, which suppresses switching noise without increasing device area or manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the switching frequency is increased to downsize power supply circuits, then the size of passive devices is reduced, but switching loss increases and power supply efficiency decreases
Solution Approach 1:
The patent changes the electrical parameters by introducing a p-type layer with specific impurity concentration (1×10^16 to 1×10^18 atoms/cm³) under the gate electrode, which modifies the gate-drain capacitance characteristics to reduce switching loss while maintaining high-frequency operation
2Speed
If the gate length is shortened to reduce gate capacitance and increase switching speed, then the switching speed is improved, but resonance between parasitic inductance and capacitance increases causing high-frequency noise
Solution Approach 1:
The patent modifies the capacitance parameter by adding a p-type layer with controlled impurity concentration under the gate electrode, which increases gate-drain capacitance to suppress resonance between parasitic inductance and capacitance, thereby reducing high-frequency noise while maintaining fast switching speed
Solution Approach 2:
The p-type layer acts as an intermediary structure between the gate electrode and the drain region, mediating the electrical characteristics to suppress noise without compromising switching performance
3Object-generated harmful factors
If a p-type layer is provided under the gate electrode to increase gate-drain capacitance and reduce switching noise, then switching noise is reduced, but the manufacturing process becomes complicated
Solution Approach 1:
The patent merges the formation of the p-type layer with existing manufacturing processes by integrating it into the semiconductor substrate preparation stage, using standard diffusion or implantation techniques that are already part of the CMOS fabrication process, thereby avoiding additional complex manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively reduces switching noise by increasing gate-drain capacitance and internal gate resistance, maintaining high reliability and low manufacturing costs while preventing resonance and high-frequency noise.
Implementation Method 1
Such a structure increases the gate-drain capacitance when a high voltage is applied, whereby temporal variation of the drain voltage (dV/dt) is reduced. Accordingly, switching noise is reduced.
Implementation Method 2
reducing the gate capacitance to increase the speed causes resonance between the parasitic inductance included in the wiring and the switching device capacitance. Accordingly, high-frequency noise is generated from the MOS gate device at the time of switching.
Implementation Method 3
A semiconductor device structure with a gate electrode provided under the gate pad electrode, incorporating a high internal gate resistance and adjusted gate-drain capacitance, which suppresses switching noise without increasing device area or manufacturing complexity.
Data Source
AI summary
A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.