3D Semiconductor Gate Electrode Formation via Sacrificial Layer Removal
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Solution Overview
Problem
The existing manufacturing process for three-dimensional nonvolatile memory devices is cumbersome and prone to damage from reaction gases, degrading the characteristics of the memory device due to the replacement of nitride layers with conductive layers.
Innovation Solution
A semiconductor device and manufacturing method involving channel layers intersecting in two directions, with stacked insulating and metal layers, where sacrificial layers are alternately formed and removed to create gate electrodes and lines, reducing voids and gas retention, thus stabilizing the structure and improving characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If nitride layers are replaced with conductive layers in the existing manufacturing process, then gate electrodes are formed, but the process becomes cumbersome and reaction gases remain in the stacked structure causing damage to peripheral layers
Solution Approach 1:
The patent extracts and removes the harmful reaction gases from the stacked structure during the manufacturing process. By introducing a removal step that specifically targets and eliminates trapped reaction gases, the harmful effects on peripheral layers are prevented while maintaining the gate electrode formation process.
Solution Approach 2:
The patent converts the potentially harmful reaction gases into a beneficial process by controlling their removal. The reaction gases that would otherwise damage peripheral layers are systematically evacuated through controlled openings and removal steps, transforming a harmful byproduct into a manageable aspect of the manufacturing process.
2Reliability
If the existing replacement process is used to form gate electrodes, then conductive layers are created, but device characteristics are degraded due to gas retention and process complexity
Solution Approach 1:
The patent segments the manufacturing process into distinct, manageable steps: forming sacrificial layers, forming openings, removing sacrificial layers, forming gate electrodes, and removing reaction gases. This segmentation simplifies the overall complex process by breaking it down into sequential, controllable operations that improve device characteristics.
Solution Approach 2:
The patent performs preliminary actions by first forming sacrificial layers and openings before forming the gate electrodes. This preliminary preparation ensures that the structure is ready to receive the conductive material properly, preventing gas trapping and ensuring good electrical contact, thereby improving device reliability.
3Manufacturing precision
If sacrificial layers are completely removed to form gate electrodes, then gate structures are created, but voids and gas retention occur in the stacked structure
Solution Approach 1:
The patent uses sacrificial layers as intermediary elements that temporarily occupy the space where gate electrodes will be formed. These sacrificial layers mediate the formation process by providing a template for precise gate electrode placement, then are systematically removed in controlled steps that prevent void formation and gas retention.
Solution Approach 2:
The patent maintains continuity of useful action by performing the sacrificial layer removal and gate electrode formation in a continuous, controlled sequence. The process ensures that openings are maintained open and gases are continuously evacuated throughout the formation process, preventing voids and maintaining structural stability.
Data Source
AI summary
A semiconductor device includes channel layers arranged in a first direction and a second direction intersecting the first direction; stacked insulating layers surrounding sidewalls of the channel layers; stacked gate electrodes interposed between the insulating layers, the gate electrodes respectively surrounding the channel layers; and stacked gate lines interposed between the insulating layers, the gate lines electrically connecting the gate electrodes to each other.