Semiconductor Gate Electrode Fabrication via Segmented Conductive Layers
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high-speed and high-integration performance due to limitations in the fabrication process, particularly in forming gate electrodes with optimal work functions and resistivity for CMOS transistors.
Innovation Solution
A method of fabricating semiconductor devices involves forming interlayer dielectrics, conducting etching processes to create specific gate electrode structures, and using different conductive layers with varying resistivities to optimize the work function and reduce resistance, ensuring reliable and efficient transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single conductive layer is formed to fill the opening, then the fabrication process is simple, but the work function and resistivity cannot be optimized for different transistor types
Solution Approach 1:
The gate electrode is divided into multiple segments (first conductive layer and second conductive layer) with different materials and properties. The first conductive layer provides work function optimization while the second conductive layer provides low resistivity, allowing each segment to fulfill a specific functional requirement that cannot be achieved by a single material.
Solution Approach 2:
Different regions of the gate electrode are assigned different materials with specific properties. The first conductive layer is positioned to provide the required work function for the semiconductor region, while the second conductive layer is positioned to minimize resistance in critical areas, creating local optimization of electrical properties throughout the structure.
2Speed
If multiple conductive layers with different materials are used, then optimal work function and resistivity are achieved, but the fabrication process complexity increases
Solution Approach 1:
The first conductive layer is formed in advance to establish the work function requirements, followed by the formation of the second conductive layer to reduce resistance. This sequential approach allows each layer to be optimized for its specific function before the next layer is added, achieving high-speed performance through systematic material selection and placement.
3Manufacturing precision
If the conductive layer is etched to expose the bottom surface, then the gate electrode structure is precisely formed, but additional etching steps are required
Solution Approach 1:
The etching process is segmented into multiple steps: first etching to expose the bottom surface of the first opening, and second etching to remove portions of conductive layers from the second opening. This segmented approach allows precise control over the gate electrode structure formation, ensuring that each conductive layer is positioned with high precision relative to the substrate and interlayer dielectric.
Data Source
AI summary
A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.