Semiconductor Gate Electrode Surrounding Wire Pattern
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to increase integration density while maintaining low production costs and improving the quality of semiconductor products, which requires scaling down semiconductor devices without compromising performance.
Innovation Solution
A semiconductor device design featuring a fin-type pattern on a substrate with a gate electrode that surrounds a wire pattern, where the gate electrode has a portion overlapping with the fin-type pattern and another portion extending around it, reducing channel roughness and enhancing electric charge mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scaling-down is performed to increase integration density, then integration density is improved, but manufacturing precision and quality control become more difficult
Solution Approach 1:
The gate electrode transitions from a planar 2D structure to a 3D surrounding structure that envelops the wire pattern channel from multiple directions. This dimensional change allows for better control of the channel region at scaled dimensions, improving quality control while maintaining high integration density through efficient space utilization.
Solution Approach 2:
The gate electrode is configured to surround and nest around the wire pattern channel region, with the gate structure containing the channel within its encompassing geometry. This nested arrangement enables precise control of the channel at scaled dimensions while maximizing the use of available space for higher integration density.
2Reliability
If the gate electrode completely surrounds the wire pattern, then channel mobility is improved, but device complexity increases
Solution Approach 1:
The gate electrode is divided into multiple segments: a first gate electrode portion and a second gate electrode portion, with the wire pattern channel positioned between them. This segmentation achieves the benefit of improved channel mobility through surrounding gate control while reducing fabrication complexity compared to a fully continuous surrounding gate structure.
Solution Approach 2:
The gate electrode structure provides different levels of surrounding control at different locations: the first gate electrode portion surrounds the wire pattern from one side, the second gate electrode portion surrounds from the opposite side, and the top surface of the wire pattern remains exposed. This local variation in gate coverage optimizes channel mobility where needed while simplifying the overall device structure.
Data Source
AI summary
A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.