Semiconductor Gate Electrode Work Function Optimization
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Solution Overview
Problem
In semiconductor devices with N-channel and P-channel insulated gate field effect transistors, it is challenging to form gate electrodes using different conductive materials that meet the requirements of having favorable work function values, high etching selection ratios, and sufficient resistance against chemical treatments, especially as the gate length decreases, leading to increased electric resistance.
Innovation Solution
The semiconductor device employs a structure where the gate electrodes of N-channel and P-channel transistors are formed using distinct conductive materials for the bottom and side parts, with protective layers of electric conductivity on top, allowing for the use of a single material for the gate electrode contact plugs and source/drain region contact plugs, simplifying the manufacturing process and optimizing the selection of conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different conductive materials are used for NMOS and PMOS gate electrodes to achieve favorable work function values, then threshold voltage symmetry is improved, but manufacturing complexity increases due to requiring multiple material deposition processes
Solution Approach 1:
The patent applies local quality by forming different conductive material layers in different regions: a first conductive material layer is formed in the NMOS region while a second conductive material layer is formed in the PMOS region. This allows each transistor type to have gate electrodes with locally optimized work function values, achieving threshold voltage symmetry while managing manufacturing complexity through region-specific material selection.
2Productivity
If gate length is reduced to increase integration degree, then device density is improved, but electric resistance of gate electrodes increases
Solution Approach 1:
The patent employs composite materials by stacking multiple conductive material layers (first conductive material layer, second conductive material layer, and optional third conductive material layer) to form the gate electrode structure. This composite approach allows optimization of both work function characteristics and electrical conductivity, addressing the increased resistance issue that arises from gate length reduction while maintaining high integration degree.
3Manufacturing precision
If conductive material layers are formed for both NMOS and PMOS gate electrodes, then work function optimization is improved, but manufacturing time increases due to sequential deposition processes
Solution Approach 1:
The patent applies segmentation by dividing the gate electrode formation into distinct conductive material layers that can be selectively formed and processed. The first conductive material layer and second conductive material layer are deposited in a segmented manner corresponding to NMOS and PMOS regions, allowing for optimized work function control while enabling parallel processing opportunities and reducing overall manufacturing time compared to forming all layers sequentially across the entire wafer.
Data Source
AI summary
A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.