Semiconductor Gate Fabrication with Simultaneous Dummy Gate Removal
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Solution Overview
Problem
The conventional semiconductor device fabrication method using gate-last processing technology and high dielectric constant gate insulating dielectric is complex and costly, making it unsuitable for large-scale production due to the need for sequential removal of dummy gates and potential damage to oxide layers during etching.
Innovation Solution
A method that simplifies the process by simultaneously removing I/O and core dummy gates, forming a mask layer between the dummy gates and oxide layers to protect the oxide layers during etching, and using specific etching solutions to minimize damage, thereby reducing the number of fabrication steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential removal of dummy gates is performed to protect oxide layers, then oxide layer damage is prevented, but fabrication process complexity and cost increase
Solution Approach 1:
A mask layer is introduced as an intermediary protective layer between the dummy gates and oxide layers. This mask layer allows simultaneous removal of both dummy gates while protecting the oxide layers from etching damage, eliminating the need for sequential removal steps.
Solution Approach 2:
The removal of I/O dummy gate and core dummy gate is merged into a single simultaneous etching step. The mask layer enables both dummy gates to be removed at the same time while protecting underlying oxide layers, simplifying the fabrication process.
2Reliability
If sequential dummy gate removal is used, then oxide layer integrity is maintained, but manufacturing cost increases
Solution Approach 1:
The mask layer serves as a cost-effective intermediary that protects oxide layers during simultaneous dummy gate removal. This single protective layer replaces multiple sequential processing steps, reducing manufacturing cost while maintaining oxide layer integrity.
Solution Approach 2:
The etching selectivity parameters are optimized to allow the etching solution to remove dummy gates efficiently while the mask layer protects oxide layers. This parameter optimization enables simultaneous removal without damage, reducing manufacturing cost.
3Productivity
If simultaneous dummy gate removal is performed without protection, then fabrication steps are reduced, but oxide layer damage occurs
Solution Approach 1:
The mask layer acts as a protective intermediary that enables simultaneous dummy gate removal without damaging oxide layers. It selectively protects the oxide layers while allowing the etching solution to access and remove the dummy gates.
Solution Approach 2:
The mask layer is selectively positioned only where oxide layer protection is needed, allowing simultaneous etching of dummy gates in regions covered by the mask while protecting underlying oxide layers. This local protection approach maintains fabrication efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces manufacturing costs, and protects the oxide layers from etching damage, making it more viable for large-scale semiconductor device production.
Implementation Method 1
etching to remove the core oxide layer
Implementation Method 2
forming a mask layer between the dummy gates and oxide layers to protect the oxide layers during etching
Data Source
AI summary
A method for fabricating a semiconductor device comprises providing a substrate having a core oxide layer and an I/O oxide layer formed thereon. The I/O oxide layer has an I/O mask layer formed thereon. The method also includes forming an I/O dummy gate on the I/O mask layer and a core dummy gate on the core oxide layer, forming an etch barrier layer on the substrate covering the dummy gates, forming a dielectric layer on the etch barrier layer, and planarizing the etch barrier layer and the dielectric layer to expose the top surface of the dummy gates. The method further includes simultaneously removing the I/O and core dummy gates to form I/O and core gate grooves, removing the core oxide layer, removing the I/O mask layer, depositing a dielectric layer in the core gate groove, and forming a metal gate layer filling the I/O and core gate grooves.