Semiconductor Gate Structure Using Fluidic Sacrificial Layer
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Solution Overview
Problem
The existing manufacturing processes for semiconductor structures in non-volatile memory devices face challenges with poor thickness uniformity and high surface roughness of sacrificial layers, requiring complex and time-consuming etching operations, and often result in incomplete removal and surface defects.
Innovation Solution
A method involving the use of a fluidic sacrificial material with low viscosity to form a planar surface, followed by a single etching step using a common etchant to remove the sacrificial layer and semiconductor layer portions, forming gate structures with improved surface smoothness and reducing the complexity of the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional sacrificial layers are used, then the manufacturing process can proceed, but the thickness uniformity is poor and surface roughness is high
Solution Approach 1:
The patent changes the physical-chemical parameters of the sacrificial layer by using a fluidic material with low viscosity instead of conventional solid or high-viscosity materials. This parameter change enables the sacrificial layer to self-planarize and achieve uniform thickness, directly resolving the contradiction between manufacturing precision and process complexity
Solution Approach 2:
The patent applies hydraulic principles by using a fluidic sacrificial material that flows and self-levels to achieve planar surfaces. The fluid properties allow the material to automatically conform to the substrate topology and achieve uniform thickness without complex deposition control, improving manufacturing precision while simplifying the process
2Productivity
If conventional etching operations are used, then the sacrificial layer can be removed, but the process is complex and time-consuming
Solution Approach 1:
The patent merges the removal of the sacrificial layer with the formation of the gate structure by using a single etching step that simultaneously removes both. This consolidation of operations directly addresses the contradiction by reducing process complexity while maintaining or improving productivity
Solution Approach 2:
The patent makes the etching process universal by selecting an etchant that can remove multiple different materials (sacrificial layer and semiconductor layer portions) with a single process step. This multi-functionality eliminates the need for multiple specialized etching steps, reducing both complexity and time
3Reliability
If conventional sacrificial layers are used, then the process can continue, but incomplete removal and surface defects occur
Solution Approach 1:
The patent employs a self-service mechanism where the fluidic sacrificial material automatically planarizes itself through its low viscosity and flow properties. This self-planarization ensures complete removal without residues and produces smooth surfaces, simultaneously improving reliability and manufacturing precision
Solution Approach 2:
By changing the physical state and viscosity parameters of the sacrificial material to a fluidic state, the patent enables complete and clean removal without surface defects. The fluid properties ensure thorough etching while maintaining surface smoothness, resolving the contradiction between complete removal and surface quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs and time, and achieves lower surface roughness of the semiconductor layer, leading to more efficient and robust semiconductor structures for memory devices.
Implementation Method 1
forming a sacrificial layer over the semiconductor layer to form a planar surface over the substrate
Implementation Method 2
forming a planar surface over the substrate
Implementation Method 3
removing the sacrificial layer, a portion of the semiconductor layer and a portion of each first isolation structure to form at least one first gate structure using the same etchant
Data Source
AI summary
A method for forming a semiconductor structure includes providing a substrate including a plurality of first isolation structures formed therein, wherein the first isolation structures are protruded from a surface of the substrate; conformally forming a semiconductor layer over the substrate and the first isolation structures; forming a sacrificial layer over the semiconductor layer to form a planar surface over the substrate; and removing the sacrificial layer, a portion of the semiconductor layer and a portion of each first isolation structure to form at least one first gate structure using a same etchant.