Semiconductor Gate Footing Control via Spacer Width Optimization
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing footing features at the interface between gate structures and substrates, which lead to non-uniform channel lengths and deteriorated device performance due to non-optimal etching operations and incomplete cleaning, affecting the proximity of epitaxy regions and device uniformity across wafers.
Innovation Solution
A semiconductor structure and method are developed to control and reduce the dimension of the footing region by using a high-k dielectric material and spacer layers, with specific etching operations to form an offset sidewall profile, allowing for precise measurement and control of footing length and spacer width, thereby optimizing the proximity of epitaxy regions and channel lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching operations are used to form gate structures, then the gate structure can be formed, but footing features are created at the interface between gate structures and substrates leading to non-uniform channel lengths
Solution Approach 1:
A footing removal layer is formed at the interface between the gate structure and substrate before completing the gate structure formation. This preliminary action prevents footing features from forming in the first place, ensuring uniform channel lengths across all transistors on the wafer.
Solution Approach 2:
The footing removal layer is selectively removed after serving its protective function during etching. This extraction eliminates the harmful footing features that would otherwise remain at the gate-substrate interface, resolving the contradiction between forming the gate structure and preventing footing.
2Reliability
If the footing region dimension is not controlled, then manufacturing is simpler, but device performance deteriorates due to non-uniform channel lengths and poor electrical uniformity across wafers
Solution Approach 1:
The footing removal layer acts as an intermediary element during the manufacturing process. It temporarily occupies the footing region, prevents etching from creating non-uniformities, and is then removed. This mediator approach ensures uniform channel lengths and device performance without requiring complex process modifications.
3Manufacturing precision
If epitaxy regions are not properly positioned relative to the gate structure, then processing is simpler, but channel length uniformity and device performance are affected
Solution Approach 1:
The footing removal layer is formed before epitaxial growth occurs. This preliminary structure provides a reference plane that ensures epitaxy regions are positioned at the correct proximity to the gate structure, achieving uniform channel lengths without requiring complex post-processing adjustments.
Data Source
AI summary
The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.