Semiconductor Gate Structure With Lower Fringing Capacitance
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Solution Overview
Problem
The switching speed of transistors is adversely affected by parasitic capacitance, particularly fringing capacitance, between the gate and source/drain due to the large area of the gate surfaces in conventional transistor structures.
Innovation Solution
A semiconductor structure is designed with a gate having reduced surface areas proximate to the source and drain, utilizing a method that includes forming a patterned structure with fin-type FETs, where the gate is separated from the source and drain by dielectric material, and using sacrificial layers and patterning techniques to reduce the fringing capacitance, allowing for the formation of semiconductor units with specific channel features and electrically conductive capping features to minimize capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate surface area is increased to improve control over the channel, then the gate-to-source/drain parasitic capacitance increases, but the switching speed deteriorates
Solution Approach 1:
The gate is segmented into multiple sections along the channel length, with each section having independently controllable surface area. This allows the gate to maintain adequate control over the channel while reducing the total gate-to-source/drain overlap area, thereby lowering parasitic capacitance and improving switching speed.
Solution Approach 2:
Different regions of the gate have different surface areas optimized for their specific functions. The gate sections closer to the source and drain have reduced surface areas to minimize parasitic capacitance, while maintaining sufficient control in the critical channel region. This local optimization resolves the contradiction between overall control and local capacitance reduction.
2Ease of manufacture
If conventional transistor structures are used with large gate surfaces, then manufacturing is simplified, but fringing capacitance increases adversely affecting performance
Solution Approach 1:
The gate structure is divided into multiple segments that can be formed using standard lithography and deposition processes. This segmentation approach maintains compatibility with conventional manufacturing techniques while enabling reduced gate surface areas to minimize fringing capacitance.
Solution Approach 2:
The gate structure transitions from a two-dimensional planar configuration to a three-dimensional segmented architecture. This dimensional change allows for reduced surface area in critical regions while maintaining effective channel control, thereby reducing fringing capacitance without sacrificing manufacturability.
Data Source
AI summary
A semiconductor structure includes two source/drain features spaced apart from each other, at least one channel feature disposed between the two source/drain features, a gate dielectric layer disposed on the at least one channel feature, a gate feature, and an electrically conductive capping feature. The gate feature is disposed on the gate dielectric layer and has a first surface, a second surface which is opposite to the first surface, and an interconnect surface which interconnects the first and second surfaces. The electrically conductive capping feature is in direct contact with one of the first and second surfaces of the gate feature, and extends beyond the interconnect surface of the gate feature. Methods for manufacturing the semiconductor structure are also disclosed.