Semiconductor Gate Structure With Graded P-Region for Low On-Resistance
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Solution Overview
Problem
Power semiconductor devices with thick p+-type semiconductor regions experience increased on resistance, while thin regions lead to unreliable gate insulation film dimensions and electric field mitigation issues.
Innovation Solution
A semiconductor device structure with a p-type semiconductor region facing the gate insulation film across a p+-type semiconductor region, where the impurity concentration of the p-type region is lower than that of the p+-type region, reducing on resistance and enhancing gate insulation film reliability by alternately disposing n-type and p-type regions to mitigate the electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the p+-type semiconductor region is made thick, then the electric field mitigation effect is improved, but the on resistance increases
Solution Approach 1:
The invention divides the semiconductor region into multiple layers: a p-type semiconductor region and a p+-type semiconductor region. The p-type region with lower impurity concentration is positioned to face the gate insulation film, while the p+-type region with higher impurity concentration is positioned deeper in the drift region. This segmentation allows each layer to perform its specific function: the p-type region mitigates the electric field at the gate insulation interface, while the p+-type region provides low resistance current conduction paths.
Solution Approach 2:
The invention applies different impurity concentrations to different spatial locations. The p-type semiconductor region has a lower impurity concentration specifically where it faces the gate insulation film to optimize electric field distribution, while the p+-type semiconductor region has a higher impurity concentration in the drift region to provide low resistance current spreading. This local differentiation of material properties resolves the contradiction between electric field mitigation and resistance reduction.
2Object-affected harmful factors
If the p+-type semiconductor region is made thin, then the on resistance is reduced, but the gate insulation film reliability degrades due to dimensional variation
Solution Approach 1:
The invention segments the semiconductor structure into distinct p-type and p+-type regions with different functions. The p-type region specifically addresses the gate insulation film reliability by providing electric field mitigation with controlled thickness, while the p+-type region independently provides low resistance current paths. This segmentation allows the p-type region to be optimized for reliability without being constrained by resistance requirements.
Solution Approach 2:
The invention creates local quality differentiation by positioning the p-type semiconductor region with lower impurity concentration adjacent to the gate insulation film, where electric field control is critical for reliability. The p+-type region with higher impurity concentration is positioned in the drift region where low resistance is paramount. This spatial differentiation of material properties allows each region to be optimized for its specific function.
3Reliability
If alternating n-type and p-type regions are disposed, then the electric field is mitigated, but the device structure becomes more complex
Solution Approach 1:
The invention segments the drift region into alternating n-type and p-type semiconductor regions, creating a structured pattern that systematically mitigates the electric field across the gate insulation film. This segmentation provides a regular, predictable structure that is easier to manufacture and control compared to irregular configurations, balancing reliability improvement with manufacturing feasibility.
Data Source
AI summary
A semiconductor device according to an embodiment includes a gate electrode extending in a first direction, a gate insulation film that covers the gate electrode, a first semiconductor region of a first conductivity type extending in a second direction orthogonal to the first direction below the gate insulation film, and a second semiconductor region of the first conductivity type that faces the gate insulation film across the first semiconductor region. An impurity concentration of the first conductivity type of the second semiconductor region is lower than that of the first semiconductor region.