Semiconductor Gate Planarization via Hard Mask Etching
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Solution Overview
Problem
In semiconductor processes, the thickness difference between NMOS and PMOS transistor gates leads to misalignment and degradation of static random access memory (SRAM) performance due to complex lithography processes and residual spacer issues, causing over-etching or under-etching of cap layers.
Innovation Solution
A semiconductor process where a hard mask layer made of a different material than the cap layers is used to cover both gates, allowing for uniform etching to achieve equal gate heights, ensuring complete removal of the hard mask and spacers without exposing the gate layers, and enabling planarization of interdielectric and contact etch stop layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a lithography process is additionally performed to thin the cap layer of the NMOS transistor, then the thickness difference between gates is reduced, but the process complexity increases and misalignment occurs at the boundary between NMOS and PMOS transistors
Solution Approach 1:
The patent applies preliminary action by forming a common cap layer structure on both NMOS and PMOS gates before any thinning operations. The cap layer is formed uniformly across both transistor types in advance, establishing a baseline that prevents subsequent misalignment issues. This preliminary uniform formation eliminates the need for complex additional lithography processes to correct thickness differences.
Solution Approach 2:
The patent implements local quality by selectively removing the cap layer only from the PMOS transistor region using targeted etching processes, while preserving the cap layer on NMOS gates. This localized treatment approach achieves the necessary thickness differentiation without requiring complex global lithography modifications, thereby maintaining process simplicity while achieving precise gate thickness control.
2Manufacturing precision
If the cap layer of the PMOS transistor is over-etched, then the thickness difference is reduced, but the gate layer below the cap layer may be exposed or the first spacer may not be removed completely
Solution Approach 1:
The patent uses the first spacer as an intermediary element that protects the gate layer during the cap layer etching process. The spacer acts as a physical barrier and etch stop layer, preventing direct exposure of the underlying gate layer even when the cap layer is being removed. This intermediary structure enables controlled removal of the cap layer while maintaining process reliability and preventing over-etching damage.
Solution Approach 2:
The patent applies beforehand cushioning by designing the etching process with built-in stop layers and controlled etch depths. The process parameters are predetermined to stop etching before reaching the gate layer, providing a cushioning effect that prevents accidental exposure. This prior cushioning through process design ensures that even with variations in etching conditions, the gate layer remains protected.
3Adaptability or versatility
If different materials are used for NMOS and PMOS epitaxial layers, then transistor performance is optimized, but the cap layer etching process becomes complex and causes thickness differences between gates
Solution Approach 1:
The patent applies segmentation by separating the cap layer into distinct regions corresponding to NMOS and PMOS transistors. This segmentation allows for selective processing of each region with appropriate etching parameters tailored to the specific transistor type and its epitaxial layer material. By dividing the processing into region-specific steps, the patent achieves optimized transistor performance while managing process complexity through systematic segmentation rather than attempting a single complex global process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process ensures uniform gate thickness, prevents misalignment, and enhances the electrical performance and yield of SRAM by eliminating residual spacer issues and planarizing the contact etch stop layer, thereby improving processing efficiency.
Implementation Method 1
An etching process is performed to entirely remove the hard mask layer remaining and the first spacer
Implementation Method 2
the epitaxial layer is formed in the recess
Data Source
AI summary
A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.