Semiconductor Gate Height Preservation via Capping Layer

Solution Overview

Problem

Conventional semiconductor device manufacturing processes face challenges in maintaining sufficient gate height due to spacer loss, which adversely affects the electrical characteristics of the device.

Innovation Solution

The method involves forming a capping layer over the gates and insulation, filling recesses with insulating depositions, and aligning their upper surfaces with the top surface of the insulation, thereby ensuring sufficient gate height and complete profiles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional gate forming process is used, then manufacturing process is simple, but gate height is insufficient due to spacer loss

Engineering Contradiction:

Improvegate heightVSAvoidmanufacturing process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming a capping layer over the gates and insulation before final processing, and pre-fills the recesses with insulating depositions. This preliminary preparation prevents spacer loss and ensures sufficient gate height are maintained throughout subsequent manufacturing steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The capping layer serves as an intermediary element between the gates/insulation and the final structure. It protects the gates during processing and prevents spacer loss. The insulating depositions filled in recesses act as intermediaries to restore and maintain the required gate height, mediating between the damaged structure and the final functional device.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If gate height is increased to improve electrical characteristics, then electrical performance is improved, but manufacturing process becomes more complex

Engineering Contradiction:

Improveelectrical characteristicsVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming a capping layer over the gates and insulation before final processing, and pre-fills the recesses with insulating depositions. This preliminary preparation prevents spacer loss and ensures sufficient gate height are maintained throughout subsequent manufacturing steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The capping layer serves as an intermediary element between the gates/insulation and the final structure. It protects the gates during processing and prevents spacer loss. The insulating depositions filled in recesses act as intermediaries to restore and maintain the required gate height, mediating between the damaged structure and the final functional device.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If capping layer and insulating depositions are added to prevent gate height loss, then gate height is sufficient, but manufacturing steps increase

Engineering Contradiction:

Improvegate heightVSAvoidmanufacturing efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The method merges multiple functions into the capping layer and insulating depositions structure. The capping layer simultaneously protects gates, defines boundaries, and provides a base for insulating depositions. The insulating depositions both fill recesses and restore gate height, combining multiple corrective actions into a single integrated structure that improves efficiency despite added steps.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively addresses the issue of gate height loss, resulting in semiconductor devices with improved electrical characteristics and simplified manufacturing processes, increasing production yield and controlling costs.

Implementation Method 1

a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS9384996B2Method for manufacturing semiconductor device and device manufactured by the same

Publication Date: 2016.07.05 UNITED MICROELECTRONICS CORP

AI summary

A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.