Semiconductor Gate Electrode Height Adjustment for Yield
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Solution Overview
Problem
Current semiconductor device manufacturing methods for nonvolatile memory devices face challenges in maximizing performance and manufacturing yield, particularly in the formation and integration of gate electrodes and charge storage structures.
Innovation Solution
The method involves forming a dummy gate electrode and a memory gate electrode with an internal charge storage portion, where the memory gate electrode is adjusted to be lower in height than the dummy gate electrode, and subsequent polishing and replacement with a metal gate electrode, allowing for improved performance and yield through precise structural adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode height is reduced to improve performance and manufacturing yield, then data retention reliability is improved and voltage requirements are reduced, but the gate electrode structure becomes more complex requiring dummy gate electrodes and selective polishing
Solution Approach 1:
The gate electrode structure is segmented into two types: dummy gate electrodes with higher height and memory gate electrodes with lower height. This segmentation allows selective treatment during manufacturing, where the dummy gates serve as placeholders or reference structures while the memory gates provide the actual storage function with optimized electrical characteristics.
Solution Approach 2:
Dummy gate electrodes are formed in advance alongside the memory gate electrodes during the same fabrication process. These dummy gates perform preliminary functions such as defining process parameters, serving as etch masks, or providing structural support during subsequent manufacturing steps before the final memory gate structure is completed.
2Manufacturing precision
If selective polishing is used to expose dummy gate electrodes while protecting memory gate electrodes, then manufacturing precision is improved, but process complexity and time increase
Solution Approach 1:
The dummy gate electrodes and memory gate electrodes are given different local qualities in terms of height and material composition. This allows the polishing process to selectively remove material from dummy gates while preserving memory gates, achieving precise selective exposure through the inherent physical differences between the two electrode types.
Solution Approach 2:
The height parameter of the dummy gate electrodes is deliberately changed to be greater than that of the memory gate electrodes. This parameter difference creates a built-in stop condition for the polishing process, automatically limiting the polishing depth to expose only the dummy gates while leaving the memory gates protected at their lower height level.
3Productivity
If dummy gate electrodes are removed and replaced with metal gate electrodes, then device performance is improved, but manufacturing steps and complexity increase
Solution Approach 1:
The dummy gate electrodes are designed as temporary, disposable structures that are removed after serving their preliminary function. They are replaced by the final metal gate electrodes which provide the actual device performance. The dummy gates are sacrificed to enable the formation of the high-performance metal gate structure.
Solution Approach 2:
The dummy gate electrodes are discarded after completing their temporary role in the manufacturing process. Their removal creates space and allows for the recovery and formation of the metal gate electrode structure, which then assumes the functional role of the gate in the final device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and manufacturing yield of semiconductor devices by optimizing the gate electrode structure and charge storage capabilities, leading to improved data retention and reduced voltage requirements for write/erase operations.
Implementation Method 1
a first gate electrode for a memory cell is formed over the semiconductor substrate via a second insulating film having an internal charge storage portion
Data Source
AI summary
Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.