Semiconductor Gate Insulating Film Formation Order
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with nonvolatile memory elements face challenges in ensuring the reliability of gate insulating films, particularly due to variations in film thickness and oxidation effects, which affect the performance and reliability of both memory elements and MISFETs.
Innovation Solution
A method is developed where the gate insulating films for memory elements and MISFETs are formed with different thicknesses using a specific order of film formation, where the thicker insulating film GF1 is formed first, followed by the thinner insulating film MZ, and then the even thinner insulating film GF2, allowing precise control and minimizing the influence of oxidation effects on the memory element's insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate insulating films are formed with different thicknesses for memory elements and MISFETs, then the performance and reliability of both device types are improved, but the manufacturing process complexity increases due to multiple film formation steps
Solution Approach 1:
The gate insulating film formation process is segmented into three distinct steps: first forming a thick insulating film (5-20 nm) for MISFET regions, then forming a thin insulating film (1-5 nm) for memory element regions, and finally forming an intermediate insulating film. This segmentation allows each region to have optimized film thickness for its specific function, improving device reliability while managing manufacturing complexity through systematic process division
Solution Approach 2:
Different regions of the semiconductor device are given different film thickness characteristics: the MISFET gate insulating film is formed thicker (5-20 nm) to ensure stability and prevent leakage, while the memory element gate insulating film is formed thinner (1-5 nm) to achieve desired electrical characteristics. This local quality differentiation optimizes performance for each device type within the same manufacturing process
2Reliability
If the gate insulating film for memory elements is made thinner, then the electrical characteristics and performance are improved, but the film becomes more susceptible to oxidation effects and manufacturing variations
Solution Approach 1:
A thick protective insulating film (5-20 nm) is formed first in the MISFET regions before forming the thin memory element insulating film. This preliminary thick film acts as a buffer that protects the underlying structure from oxidation effects during subsequent processing steps, allowing the thin memory element film to achieve its desired electrical characteristics without being overly susceptible to oxidation
Solution Approach 2:
The process incorporates an intermediate insulating film formed between the thick MISFET film and the thin memory element film. This intermediate layer serves as a cushioning barrier that protects the thin memory element insulating film from oxidation and manufacturing variations, ensuring stable electrical characteristics while maintaining the performance benefits of the thinner film structure
3Manufacturing precision
If multiple insulating films are formed in sequence with different thicknesses, then precise control of gate insulating film characteristics is achieved, but the manufacturing time and process steps increase
Solution Approach 1:
The gate insulating film formation process is designed to simultaneously serve multiple functions: the first thick film formation step establishes the base insulating layer for MISFET regions while also providing a platform for subsequent thin film deposition; the intermediate film formation serves both as a protective barrier and as part of the final multi-layer gate insulating structure. This multi-functionality reduces the need for separate dedicated steps, improving manufacturing efficiency while maintaining precise thickness control
Solution Approach 2:
The gate insulating film structure is organized as nested layers: the thin memory element insulating film (1-5 nm) is formed within the context of the thicker MISFET insulating film structure (5-20 nm), with an intermediate film nested between them. This nested arrangement allows precise thickness control of each layer while integrating them into a unified structure, reducing the need for separate processing cycles and improving manufacturing efficiency
Data Source
AI summary
A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.