Semiconductor Gate Connection with Insulating Layer
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Solution Overview
Problem
Parasitic capacitance in power transistors, particularly in high-frequency and high-power applications like cellular base stations, limits device performance and increases resistive parasitics, necessitating the reduction of gate contacts which in turn increases series gate resistance.
Innovation Solution
The semiconductor device incorporates a layer of insulating material (STI regions) beneath the gate connection and field plate to reduce parasitic capacitance, including gate-source, gate-drain, and substrate capacitance, by providing a lower capacitive load and allowing for more gate connection regions in parallel, thereby reducing series input resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If device size increases to source and sink large currents, then power capability is improved, but parasitic capacitance increases
Solution Approach 1:
The gate connection extends in a direction toward the drain region, utilizing spatial dimensionality to create additional contact paths. This dimensional approach allows parallel current paths to be formed without increasing the vertical overlap between gate and source that would increase capacitance, thus decoupling power capability from parasitic capacitance.
Solution Approach 2:
The gate electrode structure is segmented into functional regions: the first region directly over the channel for control, and the second region (gate connection) extending toward the drain for providing parallel contact paths. This segmentation enables large current handling through multiple paths while maintaining low parasitic capacitance by limiting capacitive overlap in the control region.
2Object-affected harmful factors
If gate routing is placed over the source to maintain minimum parasitic gate-source capacitance, then capacitance is controlled, but the number of gate contacts must be reduced
Solution Approach 1:
The gate electrode is segmented into a first region for capacitance control (with minimal overlap with source) and a second region (gate connection) that provides multiple contact paths. This segmentation resolves the contradiction by separating the capacitance-control function from the contact-provision function, allowing both low gate-source capacitance and adequate number of gate contacts.
Solution Approach 2:
The gate connection acts as an intermediary structure that provides multiple contact paths without requiring traditional gate routing over the source region. This intermediary element decouples the relationship between routing placement and contact number, allowing multiple contacts to be achieved without increasing gate-source capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively minimizes parasitic capacitance, enhancing high-frequency performance and noise characteristics of power transistors by reducing capacitive loading and allowing for increased gate connection regions without increasing gate-source capacitance.
Implementation Method 1
The semiconductor device incorporates a layer of insulating material (STI regions) beneath the gate connection and field plate to reduce parasitic capacitance, including gate-source, gate-drain, and substrate capacitance
Data Source
AI summary
An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.