Semiconductor Gate Insulating Layer Thickness Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As MOS transistor feature sizes are scaled down, challenges arise in achieving improved operational properties due to the poor heat-resistant properties of metal gate electrodes and the need for varying gate insulating layer thicknesses across different device regions.
Innovation Solution
A semiconductor device is fabricated with distinct gate patterns on different substrate regions, featuring a thicker first gate insulating layer and a second gate insulating layer with a wider top width than bottom width, along with a method that includes forming dummy gate patterns, removing layers to create trenches, and depositing high-k dielectric and metal layers to form gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate insulating layer thickness is reduced to scale down MOS transistor features, then the transistor size decreases, but the gate insulating layer quality deteriorates and defects increase
Solution Approach 1:
The substrate is divided into first and second regions with different gate insulating layer thicknesses. The first region receives a thicker gate insulating layer while the second region receives a thinner gate insulating layer, allowing each region to be optimized independently for its specific device requirements without compromising overall quality
Solution Approach 2:
Different gate insulating layer thicknesses are applied to different regions of the substrate based on local device requirements. High-voltage devices in the first region use thicker gate insulating layers for better breakdown characteristics, while low-voltage devices in the second region use thinner gate insulating layers for lower operating voltages
2Reliability
If a metal layer is used for the gate electrode to achieve low resistance, then the electrical performance improves, but the heat-resistant property deteriorates
Solution Approach 1:
The gate electrode is formed as a composite structure combining a metal layer (for low resistance and high electrical performance) with a refractory metal nitride layer (for high temperature stability and heat resistance). This composite structure allows the device to benefit from both materials' advantages simultaneously
3Adaptability or versatility
If different gate insulating layer thicknesses are formed on different substrate regions to realize devices with different performance, then device versatility improves, but the fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming a thick gate insulating layer on the entire substrate, selectively removing portions in second regions, and forming thin gate insulating layers only in those regions. This segmentation allows different thicknesses to be achieved through a systematic, manageable process rather than attempting to deposit different thicknesses simultaneously across the entire substrate
Solution Approach 2:
A thick gate insulating layer is formed preliminarily across the entire substrate before any selective removal. This preliminary formation ensures uniform high-quality insulation throughout, and subsequent selective thinning in specific regions creates the desired thickness variations without requiring complex co-deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electric characteristics by enabling defect-free, high-quality gate insulating layers with different thicknesses on separate substrate regions, improving transistor performance and facilitating the formation of high-voltage and low-voltage transistors.
Implementation Method 1
cleaning the portion of the substrate exposed by the second trench using an oxide etching solution
Data Source
AI summary
Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first gate pattern on the first region, a second gate pattern on the second region, and an interlayer insulating layer enclosing the first and second gate patterns. The first gate pattern including a first gate insulating layer and a first gate electrode, the second gate pattern including a second gate insulating layer and a second gate electrode, the first gate insulating layer is thicker than the second gate insulating layer, and a top width of the second gate pattern is larger than a bottom width thereof.