Semiconductor Device Gate Insulating Layer Wet Oxidation
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Solution Overview
Problem
Thin film transistors with gate insulating layers of small thickness suffer from uneven film thickness, leading to electric field concentration, increased leak current, and reduced gate withstand voltage, particularly in high-speed operation circuits.
Innovation Solution
A semiconductor device is formed by oxidizing the end portion of the semiconductor layer using wet oxidation to create a first insulating layer, followed by the formation of a second insulating layer and a gate electrode, which reduces electric field concentration and prevents contact between the semiconductor layer and the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate insulating layer thickness is reduced to achieve high-speed operation, then the switching speed is improved, but the film thickness becomes uneven at the end portion of the semiconductor layer, causing electric field concentration and reduced reliability
Solution Approach 1:
The patent applies local quality by forming a tapered structure specifically at the end portion of the semiconductor layer, while maintaining a uniform thickness in the channel forming region. This localized structural modification ensures that the gate insulating layer achieves uniform thickness in the critical channel region (improving reliability) while the tapered end portion prevents edge effects and electric field concentration (enabling thinner overall structure for high-speed operation).
Solution Approach 2:
The patent employs preliminary action by pre-forming the tapered structure at the end portion of the semiconductor layer before depositing the gate insulating layer. This preliminary structural preparation ensures that when the thin gate insulating layer is formed, it naturally achieves uniform thickness without subsequent thickness variation, thereby preventing electric field concentration and maintaining high reliability in high-speed devices.
2Speed
If the gate insulating layer is made thin for high-speed operation, then the device speed increases, but leak current increases due to electric field concentration
Solution Approach 1:
The tapered structure is locally applied only at the end portion of the semiconductor layer, creating a gradual transition that distributes the electric field more evenly. This local modification eliminates the sharp edges that cause electric field concentration and subsequent leak current, while preserving the thin gate insulating layer necessary for high-speed operation.
3Ease of manufacture
If a conventional gate insulating layer structure is used, then the manufacturing process is simple, but the coverage is poor at the end portion of the semiconductor layer
Solution Approach 1:
The tapered structure is formed in advance during the semiconductor layer fabrication process, before gate insulating layer deposition. This preliminary action ensures that the subsequent gate insulating layer deposition automatically achieves uniform coverage without requiring complex additional process steps, thereby maintaining manufacturing simplicity while improving film thickness uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor device by reducing leak current and improving gate withstand voltage, especially when the gate insulating layer thickness is in the range of several nanometers to tens of nanometers.
Implementation Method 1
oxidizing the end portion of the semiconductor layer using wet oxidation to form a first insulating layer
Data Source
AI summary
An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.