Semiconductor Device Gate Insulation Film Foreign Matter Adherence
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Solution Overview
Problem
In semiconductor devices with high electric permittivity gate insulation films, foreign matter such as lanthanum fluoride can adhere to the sides of n-channel transistors during the patterning process, leading to performance deterioration and defects, which existing technologies do not adequately address.
Innovation Solution
The semiconductor device and manufacturing method involve forming a mixture of peripheral n-type and p-type gate structures around functional transistors, reducing the proportion of n-type gate structures in peripheral transistors to minimize the adherence of foreign matter to the n-channel transistor's gate insulation film, thereby enhancing yield and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lanthanum series insulation film of high electric permittivity is used in an n-channel transistor, then the electric permittivity of the gate insulation film is improved, but foreign matter such as lanthanum fluoride may adhere to the gate insulation film during patterning, causing performance deterioration and defects
Solution Approach 1:
The patent applies different gate structures to different regions: functional n-channel transistors use high-permittivity lanthanum series insulation films, while dummy n-channel transistors use conventional insulation films. This local differentiation allows the functional transistors to benefit from high electric permittivity while dummy transistors serve as sacrificial structures that prevent foreign matter adherence during patterning, thus resolving the contradiction between improved reliability and prevention of harmful foreign matter adherence.
2Shape
If dummy patterns are arranged at the peripheries of functional transistors to improve flatness during CMP, then the flatness of the uppermost plane is improved, but the proportion of n-channel transistors increases, leading to more foreign matter adherence issues
Solution Approach 1:
The patent differentiates the gate structure material based on transistor function and position: dummy transistors at the periphery use conventional insulation films while functional transistors use high-permittivity films. This allows dummy patterns to maintain their flatness-improving function during CMP while preventing foreign matter adherence issues in the high-permittivity film region, as the dummy structures act as protective sacrificial elements.
Solution Approach 2:
The patent converts the potential harm of having numerous n-channel dummy transistors (which would increase foreign matter adherence) into a benefit by using these dummy structures as protective barriers. The dummy transistors with conventional insulation films are positioned to shield the functional high-permittivity transistors from foreign matter contamination during patterning, thus turning what would be a harmful increase in n-channel transistor count into a protective mechanism.
Data Source
AI summary
The present invention, in a method for manufacturing a semiconductor device having an n-channel transistor and a p-channel transistor each of which has an insulation film of a high electric permittivity, inhibits a foreign matter from adhering to the side of a gate insulation film of the n-channel transistor. Over the main surface of a semiconductor substrate, a functional n-channel transistor is formed in a p-type impurity region and a functional p-channel transistor is formed in an n-type impurity region. A plurality of first peripheral transistors formed in the region other than the functional n-channel transistor in the p-type impurity region are formed so that a peripheral n-type structure and a peripheral p-type structure may coexist in a planar view.