Semiconductor Device Gate Insulation for High Withstand Voltage
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Solution Overview
Problem
The field plates in conventional nitride semiconductor devices reduce electric field concentration but lead to a decrease in withstand voltage, and the miniaturization of these devices is hindered by the need for numerous process steps.
Innovation Solution
The semiconductor device design includes a gate insulating layer extending from the source region through the semiconductor layer to the buffer layer, with a gate electrode in contact with this layer, and an isolation region between the body and drain regions, forming capacitors and diodes to prevent leakage current and electron trapping, thereby maintaining high withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If field plates are added to prevent electric field concentration, then electric field distribution is improved, but withstand voltage decreases
Solution Approach 1:
The gate electrode is divided into two distinct parts: a gate electrode portion and a field plate portion, separated by a gate insulating layer. This segmentation allows each part to perform its specific function independently - the gate electrode controls the channel while the field plate extends the electric field control to prevent concentration at the gate edge, thereby maintaining high withstand voltage while achieving uniform electric field distribution.
Solution Approach 2:
The gate insulating layer acts as an intermediary between the gate electrode portion and the field plate portion. This insulating layer enables the field plate to extend the electric field control function without directly contacting the gate electrode, preventing electric field concentration while maintaining the insulating barrier necessary for high breakdown voltage.
2Strength
If multistep field plates are arranged to improve electric field distribution, then withstand voltage is maintained, but device complexity and manufacturing steps increase
Solution Approach 1:
The gate electrode and field plate are merged into a single integrated structure where the field plate portion is formed as an extension of the gate electrode through the gate insulating layer. This unified structure eliminates the need for separate multistep field plate arrangements, reducing manufacturing complexity while maintaining effective electric field control and high withstand voltage.
Solution Approach 2:
The integrated gate electrode structure serves multiple functions simultaneously: it acts as the control electrode for the transistor channel, extends as a field plate to prevent electric field concentration, and maintains electrical insulation through the gate insulating layer. This multi-functionality eliminates the need for separate field plate structures and their associated manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures high withstand voltage and prevents current decrease, allowing for the flow of large currents without electron trapping, even under high voltage conditions, by distributing the electric field uniformly and reducing local electric field concentrations.
Implementation Method 1
the gate insulating layer 7 and the isolation region 11 form capacitors
Implementation Method 2
the semiconductor region and the body region form a diode
Implementation Method 3
the gate insulating layer is provided to extend from the surface layer of the source region via the semiconductor layer and reach at least the buffer layer
Data Source
Figure 1~2
Figure 3
Figure 4A~4B
AI summary
There is provided a semiconductor device which has a higher withstand voltage and controls current decrease. A semiconductor device 100 includes a substrate 1, a buffer layer 2 provided on the substrate 1, a semiconductor layer 3 provided on the buffer layer 2, a body region 4 provided at a part of a surface layer of the semiconductor layer 3, a source region 5 provided at a part of a surface layer of the body region 4, a drain region 6 provided at a part of the surface layer of the semiconductor layer 3 outside the body region 4, a gate insulating layer 7 provided to extend from the surface layer of the body region 4 to a predetermined depth, a gate electrode 8 provided on the gate insulating layer 7, a source electrode 9 provided on the source region 5, a drain electrode 10 provided on the drain region 6, and an isolation region 11 provided to extend from the surface layer of the semiconductor layer 3 to above the predetermined depth, the isolation region isolating the body region 4 from the drain region 6.