Semiconductor Gate Insulator Design for Breakdown Voltage
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Solution Overview
Problem
Semiconductor devices, such as MOSFETs, face challenges in maintaining high breakdown voltage and low on-resistance due to dielectric breakdown issues between the gate electrode and conductive portions, which are exacerbated by voids and uneven insulating layer formations during manufacturing.
Innovation Solution
The semiconductor device incorporates a specific insulating portion configuration with a first insulating part having a shorter length in the X-direction that becomes longer upward, and a second insulating part with a longer or constant length, positioned between the gate electrode parts, to increase the distance between the gate electrode and the conductive portion, reducing the likelihood of dielectric breakdown. This configuration involves forming insulating layers with varying boron concentrations and using polysilicon for conductive portions, and optimizing trench etching and oxidation processes to prevent voids and ensure reliable gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate electrode is positioned closer to the conductive portion to reduce on-resistance, then on-resistance decreases, but dielectric breakdown risk increases
Solution Approach 1:
An insulating portion is introduced as an intermediary between the gate electrode and the conductive portion. This insulating layer physically separates the two conductive elements, preventing direct electrical contact and dielectric breakdown while allowing the gate electrode to remain positioned optimally for low on-resistance operation.
Solution Approach 2:
The insulating portion extends in the vertical direction (thickness dimension) between the gate electrode and conductive portion. By utilizing the vertical dimension for insulation rather than increasing horizontal spacing, the design maintains low on-resistance while preventing dielectric breakdown through adequate vertical separation.
2Ease of manufacture
If a uniform insulating layer is formed between gate electrode parts, then manufacturing is simplified, but voids form due to uneven underlying surfaces
Solution Approach 1:
The insulating layer is formed with non-uniform thickness to match the uneven underlying surface topology. The insulating layer thickness is locally adjusted to compensate for surface variations, ensuring complete coverage without voids while maintaining manufacturing feasibility through a single deposition process.
Solution Approach 2:
The uneven surface is prepared in advance before forming the insulating layer. By pre-shaping the underlying surface or using a sufficiently thick insulating material that can conform to the surface, the design prevents void formation during subsequent insulating layer deposition.
Data Source
AI summary
According to one embodiment, a semiconductor device includes first and second electrodes, first, second and third semiconductor regions, a first conductive portion, a gate electrode, and a second insulating portion. The first and second semiconductor regions are provided on the first semiconductor region. The third semiconductor regions are selectively provided respectively on the second semiconductor regions. The first conductive portion is provided inside the first semiconductor region with a first insulating portion interposed. The gate electrode is provided on the first conductive portion and the first insulating portion and separated from the first conductive portion. The gate electrode includes first and second electrode parts. The second insulating portion is provided between the first and second electrode parts. The second insulating portion includes first and second insulating parts. The second electrode is provided on the second and third semiconductor regions.